CDCE62002 Series

Four output clock generator/jitter cleaner with integrated dual VCOs

Link to Manufacturer Page: https://www.ti.com/

Catalog

Four output clock generator/jitter cleaner with integrated dual VCOs

Part	Supplier Device Package	Divider/Multiplier	Package / Case	Type	Operating Temperature [Min]	Operating Temperature [Max]	Input	Frequency - Max [Max]	Voltage - Supply [Max]	Voltage - Supply [Min]	Number of Circuits	Output	Ratio - Input:Output [custom]	Ratio - Input:Output [custom]	Mounting Type	Function	Utilized IC / Part	Supplied Contents
Texas Instruments CDCE62002RHBR	32-VQFN (5x5)	Yes/No	32-VFQFN Exposed Pad	Clock Generator	-40 °C	85 °C	Crystal, LVCMOS, LVDS, LVPECL	1.175 GHz	3.6 V	3 V	1	LVCMOS, LVDS, LVPECL	2	2	Surface Mount
Texas Instruments CDCE62002RHBT	32-VQFN (5x5)	Yes/No	32-VFQFN Exposed Pad	Clock Generator	-40 °C	85 °C	Crystal, LVCMOS, LVDS, LVPECL	1.175 GHz	3.6 V	3 V	1	LVCMOS, LVDS, LVPECL	2	2	Surface Mount
Texas Instruments CDCE62002EVM				Timing												Clock Generator	CDCE62002	Board(s)

Key Features

• Frequency Synthesizer With PLL/VCO and Partially Integrated Loop FilterFully Configurable Outputs Including Frequency and Output FormatSmart Input Multiplexer Automatically Switches Between One of Two Reference InputsMultiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover ModeIntegrated EEPROM Determines Device Configuration at Power UpExcellent Jitter PerformanceIntegrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner ModeProgrammable Charge Pump Gain and Loop Filter SettingsUnique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:0.5 ps RMS (10 kHz to 20 MHz) Output Jitter PerformanceLow Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHzOutput Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer ModeLVPECL, LVDS, and LVCMOSIndependent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32Flexible Inputs With Innovative Smart Multiplexer:Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHzClock Generator Mode Using Crystal InputSmart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe OperationTypical Power Consumption 750 mW at 3.3 VIntegrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined StateOffered in QFN-32 PackageESD Protection Exceeds 2000 V HBMIndustrial Temperature Range: –40°C to +85°CAPPLICATIONSData Converter and Data Aggregation ClockingWireless InfrastructureSwitches and RoutersMedical ElectronicsMilitary and AerospaceIndustrialClock Generation and Jitter CleaningAll other trademarks are the property of their respective ownersFrequency Synthesizer With PLL/VCO and Partially Integrated Loop FilterFully Configurable Outputs Including Frequency and Output FormatSmart Input Multiplexer Automatically Switches Between One of Two Reference InputsMultiple Operational Modes Include Clock Generation Through Crystal, SERDES Start-Up Mode, Jitter Cleaning, and Oscillator Based Holdover ModeIntegrated EEPROM Determines Device Configuration at Power UpExcellent Jitter PerformanceIntegrated Frequency Synthesizer Including PLL, Multiple VCOs, and Loop Filter:Full Programmability Facilitates Phase Noise Performance Optimization Enabling Jitter Cleaner ModeProgrammable Charge Pump Gain and Loop Filter SettingsUnique Dual-VCO Architecture Supports a Wide Tuning Range 1.750 GHz to 2.356 GHz.Universal Output Blocks Support Up to 2 Differential, 4 Single-Ended, or Combinations of Differential or Single-Ended:0.5 ps RMS (10 kHz to 20 MHz) Output Jitter PerformanceLow Output Phase Noise: –130 dBc/Hz at 1 MHz Offset, Fc = 491.52 MHzOutput Frequency Ranges From 10.94 MHz to 1.175 GHz in Synthesizer ModeLVPECL, LVDS, and LVCMOSIndependent Output Dividers Support Divide Ratios for 1, 2, 3, 4, 5, 8, 10, 12, 16, 20, 24, and 32Flexible Inputs With Innovative Smart Multiplexer:Two Universal Differential Inputs Accept Frequencies from 1 MHz up to 500 MHz (LVPECL), 500 MHz (LVDS), or 250 MHz (LVCMOS)One Auxiliary Input Accepts Crystals in the Range of 2 MHz to 42 MHzClock Generator Mode Using Crystal InputSmart Input Multiplexer Can be Configured to Automatically Switch Between Highest Priority Clock Source Available Allowing for Fail-Safe OperationTypical Power Consumption 750 mW at 3.3 VIntegrated EEPROM Stores Default Settings; Therefore, the Device Can Power Up in a Known, Predefined StateOffered in QFN-32 PackageESD Protection Exceeds 2000 V HBMIndustrial Temperature Range: –40°C to +85°CAPPLICATIONSData Converter and Data Aggregation ClockingWireless InfrastructureSwitches and RoutersMedical ElectronicsMilitary and AerospaceIndustrialClock Generation and Jitter CleaningAll other trademarks are the property of their respective owners

Description

The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available. (1)10-kHz to 20-MHz integration bandwidth.(2)Frequency range depends on operational mode and output format selected. The CDCE62002 device is a high-performance clock generator featuring low output jitter, a high degree of configurability through a SPI interface, and programmable start-up modes determined by on-chip EEPROM. Specifically tailored for clocking data converters and high-speed digital signals, the CDCE62002 achieves jitter performance under 0.5 ps RMS(1). It incorporates a synthesizer block with partially integrated loop filter, a clock distribution block including programmable output formats, and an input block featuring an innovative smart multiplexer. The clock distribution block includes two individually programmable outputs that can be configured to provide different combinations of output formats (LVPECL, LVDS, LVCMOS). Each output can also be programmed to a unique output frequency (ranging from 10.94 MHz to 1.175 GHz(2)). If Both outputs are configured in single-ended mode (such as LVCMOS), the CDCE62002 supports up to four outputs. The input block includes one universal differential inputs which support frequencies up to 500 MHz and an auxiliary input that can be configured to connect to an external AT-Cut crystal through an onboard oscillator block. The smart input multiplexer has two modes of operation, manual and automatic. In manual mode, the user selects the synthesizer reference through the SPI interface. In automatic mode, the input multiplexer will automatically select between the highest priority input clock available. (1)10-kHz to 20-MHz integration bandwidth.(2)Frequency range depends on operational mode and output format selected.