CDCLVP215 Series
Dual 1:5 high speed LVPECL fan out buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Dual 1:5 high speed LVPECL fan out buffer
| Part | Ratio - Input:Output [custom] | Input | Type | Package / Case | Frequency - Max [Max] | Mounting Type | Supplier Device Package | Operating Temperature [Min] | Operating Temperature [Max] | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Output | Number of Circuits | Voltage - Supply [Max] | Voltage - Supply [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP215RHBR | 1:5 | LVECL, LVPECL | Fanout Buffer (Distribution) | 32-VFQFN Exposed Pad | 3.5 GHz | Surface Mount | 32-VQFN (5x5) | -40 °C | 85 °C | LVECL, LVPECL | 2 | 3.8 V | 2.375 V | ||
Texas Instruments CDCLVP215RHBT | 1:5 | LVECL, LVPECL | Fanout Buffer (Distribution) | 32-VFQFN Exposed Pad | 3.5 GHz | Surface Mount | 32-VQFN (5x5) | -40 °C | 85 °C | LVECL, LVPECL | 2 | 3.8 V | 2.375 V |
Key Features
• 2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock OutputsFully Compatible With LVPECL/LVECLSupports a Wide Supply Voltage Range From 2.375 V to 3.8 VOpen Input Default StateLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsVBBReference Voltage Output for Single-Ended ClockingAvailable in the QFN32 PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111APPLICATIONSDesigned for Driving 50-Transmission Lines High Performance Clock Distribution2× One Differential Clock Input Pair LVPECL to 5 Differential LVPECL Clock OutputsFully Compatible With LVPECL/LVECLSupports a Wide Supply Voltage Range From 2.375 V to 3.8 VOpen Input Default StateLow-Output Skew (Typ 15 ps) for Clock-Distribution ApplicationsVBBReference Voltage Output for Single-Ended ClockingAvailable in the QFN32 PackageFrequency Range From DC to 3.5 GHzPin-to-Pin Compatible With the MC100 Series EP111, LVEP210, ES6111, LVEP111APPLICATIONSDesigned for Driving 50-Transmission Lines High Performance Clock Distribution
Description
AI
The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50-transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLKAorCLKBand bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP215 is characterized for operation from –40°C to 85°C.
The CDCLVP215 clock driver distributes two times one differential clock pair of LVPECL, (CLKA, CLKB) to 5 pairs of differential LVPECL clock (QA0..QA4, QB0..QB4) outputs with minimum skew for clock distribution. The CDCLVP215 specifies low output-to-output skew. The CDCLVP215 is specifically designed for driving 50-transmission lines. When an output pair is not used, leaving it open is recommended to reduce power consumption. If only one of the output pairs is used, the other output pair must be identically terminated to 50.
The VBBreference voltage output is used if single-ended input operation is required. In this case, the VBBpin should be connected toCLKAorCLKBand bypassed to GND via a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP215 is characterized for operation from –40°C to 85°C.