CDCLVP1208 Series
Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer
| Part | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Mounting Type | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Frequency - Max [Max] | Operating Temperature [Min] | Operating Temperature [Max] | Voltage - Supply [Min] | Voltage - Supply [Max] | Output | Input | Number of Circuits | Type | Supplier Device Package | Package / Case |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCLVP1208RHDT | Surface Mount | 2 | 8 | 2 GHz | -40 °C | 85 °C | 2.375 V | 3.6 V | LVPECL | LVCMOS, LVDS, LVPECL, LVTTL | 1 | Fanout Buffer (Distribution), Multiplexer | 28-VQFN (5x5) | 28-VFQFN Exposed Pad | ||
Texas Instruments CDCLVP1208RHDR | Surface Mount | 2 | 8 | 2 GHz | -40 °C | 85 °C | 2.375 V | 3.6 V | LVPECL | LVCMOS, LVDS, LVPECL, LVTTL | 1 | Fanout Buffer (Distribution), Multiplexer | 28-VQFN (5x5) | 28-VFQFN Exposed Pad |
Key Features
• 2:8 Differential BufferSelectable Clock Inputs Through Control terminalUniversal Inputs Accept LVPECL, LVDS, andLVCMOS/LVTTLEight LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 73 mAVery Low Additive Jitter: <100 fs,rms in 10 kHz to20 MHz Offset Range:57 fs, rms (typical) at 122.88 MHz48 fs, rms (typical) at 156.25 MHz30 fs, rms (typical) at 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 450 psMaximum Output Skew: 20 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to 85°CSupports 105°C PCB Temperature(Measured with a Thermal Pad)ESD Protection Exceeds 2 kV (HBM)Available in 5-mm × 5-mm QFN-28 (RHD)Package2:8 Differential BufferSelectable Clock Inputs Through Control terminalUniversal Inputs Accept LVPECL, LVDS, andLVCMOS/LVTTLEight LVPECL OutputsMaximum Clock Frequency: 2 GHzMaximum Core Current Consumption: 73 mAVery Low Additive Jitter: <100 fs,rms in 10 kHz to20 MHz Offset Range:57 fs, rms (typical) at 122.88 MHz48 fs, rms (typical) at 156.25 MHz30 fs, rms (typical) at 312.5 MHz2.375-V to 3.6-V Device Power SupplyMaximum Propagation Delay: 450 psMaximum Output Skew: 20 psLVPECL Reference Voltage, VAC_REF, Availablefor Capacitive-Coupled InputsIndustrial Temperature Range: –40°C to 85°CSupports 105°C PCB Temperature(Measured with a Thermal Pad)ESD Protection Exceeds 2 kV (HBM)Available in 5-mm × 5-mm QFN-28 (RHD)Package
Description
AI
The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.
The CDCLVP1208 is a highly versatile, low additive jitter buffer that can generate eight copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1208 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 20 ps, making the device a perfect choice for use in demanding applications.
The CDCLVP1208 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to eight pairs of differential LVPECL clock outputs (OUT0, OUT7) with minimum skew for clock distribution. The CDCLVP1208 can accept two clock sources into an input multiplexer. The inputs can be LVPECL, LVDS, or LVCMOS/LVTTL.
The CDCLVP1208 is specifically designed for driving 50-Ω transmission lines. When driving the inputs in single-ended mode, the LVPECL bias voltage (VAC_REF) should be applied to the unused negative input terminal. However, for high-speed performance up to 2 GHz, differential mode is strongly recommended.
The CDCLVP1208 is packaged in a small 28-pin, 5-mm × 5-mm QFN package and is characterized for operation from –40°C to 85°C.