10KHT5574 Series
Octal ECL-to-TTL translator with D-type edge-triggered flip-flops and 3-state outputs
Manufacturer: Texas Instruments
Catalog(1 parts)
| Part | Number of Circuits▲▼ | Channel Type | Channels per Circuit▲▼ | Output Signal | Supplier Device Package | Translator Type | Input Signal | Package / Case▲▼ | Package / Case▲▼ | Package / Case | Mounting Type | Output Type | Operating Temperature▲▼ | Operating Temperature▲▼ |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
1 ul | Unidirectional | 8 ul | TTL | 24-SOIC | Mixed Signal | ECL | 0.007499999832361937 m | 0.007493000011891127 m | 24-SOIC | Surface Mount | Tri-State, Non-Inverted | 75 °C | 0 °C |
Key Features
• 10KH CompatibleECL Clock and TTL Control InputsFlow-Through Architecture Optimizes PCB LayoutCenter Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching NoisePackage Options Include "Small Outline" Packages and Standard Plastic DIPs10KH CompatibleECL Clock and TTL Control InputsFlow-Through Architecture Optimizes PCB LayoutCenter Pin VCC, VEE, and GND Configurations Minimize High-Speed Switching NoisePackage Options Include "Small Outline" Packages and Standard Plastic DIPs
Description
AI
This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output-enable inputOEdoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.
The SN10KHT5574 is characterized for operation from 0°C to 75°C.
This octal ECL-to-TTL translator is designed to provide efficient translation between a 10KH ECL signal environment and a TTL signal environment. This device is designed specifically to improve the performance and density of ECL-to-TTL CPU/bus-oriented functions such as memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The eight flip-flops of the SN10KHT5574 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic levels that were set up at the D inputs.
A buffered output-enable input (OE) can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance third state and increased drive provide the capability to drive bus lines without need for interface or pullup components.
The output-enable inputOEdoes not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are off.
The SN10KHT5574 is characterized for operation from 0°C to 75°C.