TAS5086 Series

The TAS5086 is a six-channel digital pulse-width modulator (PWM) that provides both advanced performance and a high level of system integration. The TAS5086 is designed to interface seamlessly with most audio digital signal processors and MPEG decoders, accepting a wide range of input data and clock formats. The TAS5086 drives six channels of speakers in either single-ended or bridge-tied load configurations that accept a 1N + 1 interface format. The TAS5086 also supports 2N + 1 power stages with the use of some external logic (e.g., TAS5112). Stereo line out in I2S format is available with either a pass-through signal (SDIN4) or an internal downmix. The TAS5086 uses AD modulation operating at a 384-kHz switching rate for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz data. The 8× oversampling, combined with the 4th-order noise shaper, provides a broad, flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. The TAS5086 is only an I2C slave device, which always receives MCLK, SCLK, and LRCLK from other system components. The TAS5086 accepts clock rates of 128, 192, 256, 384, and 512 fS. The TAS5086 accepts a 64-fSmaster clock for 176.4-kHz and 192-kHz data. The TAS5086 accepts a 64-fSbit clock for all data rates. The TAS5086 also can accept a 48-fSSCLK rate for MCLK ratios of 192 fSand 384 fS. The TAS5086 is composed of five functional blocks. For detailed application information, see theUsing the PurePath Digital PWM Processorapplication report (SLEA046). The TAS5086 is a six-channel digital pulse-width modulator (PWM) that provides both advanced performance and a high level of system integration. The TAS5086 is designed to interface seamlessly with most audio digital signal processors and MPEG decoders, accepting a wide range of input data and clock formats. The TAS5086 drives six channels of speakers in either single-ended or bridge-tied load configurations that accept a 1N + 1 interface format. The TAS5086 also supports 2N + 1 power stages with the use of some external logic (e.g., TAS5112). Stereo line out in I2S format is available with either a pass-through signal (SDIN4) or an internal downmix. The TAS5086 uses AD modulation operating at a 384-kHz switching rate for 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz data. The 8× oversampling, combined with the 4th-order noise shaper, provides a broad, flat noise floor and excellent dynamic range from 20 Hz to 20 kHz. The TAS5086 is only an I2C slave device, which always receives MCLK, SCLK, and LRCLK from other system components. The TAS5086 accepts clock rates of 128, 192, 256, 384, and 512 fS. The TAS5086 accepts a 64-fSmaster clock for 176.4-kHz and 192-kHz data. The TAS5086 accepts a 64-fSbit clock for all data rates. The TAS5086 also can accept a 48-fSSCLK rate for MCLK ratios of 192 fSand 384 fS. The TAS5086 is composed of five functional blocks. For detailed application information, see theUsing the PurePath Digital PWM Processorapplication report (SLEA046).