CDCBT1001 Series
1.2-V to 1.8-V clock buffer and level translator
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
1.2-V to 1.8-V clock buffer and level translator
| Part | Supplier Device Package | Frequency - Max [Max] | Mounting Type | Output | Type | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Number of Circuits | Package / Case | Input | Voltage - Supply [Min] | Voltage - Supply [Max] | Operating Temperature [Max] | Operating Temperature [Min] | Ratio - Input:Output [custom] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CDCBT1001DPWR | 5-X2SON (0.8x0.8) | 24 MHz | Surface Mount | LVCMOS | Clock Buffer | 1 | 4-XFDFN Exposed Pad | LVCMOS | 1.08 V | 1.32 V | 85 °C | -40 °C | 1:1 |
Key Features
• Clock frequency range: DC to 24 MHz1.2-V to 1.8-V LVCMOS clock level translation:VDD_IN = 1.2 V ± 10%VDD_OUT = 1.8 V ± 10%Low additive jitter and phase noise:0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout= 24 MHz)–120-dBc/Hz maximum phase noise at 1-kHz offset (fout= 24 MHz)–148-dBc/Hz maximum phase noise floor (fout= 24 MHz, foffset≥ 1 MHz)5-ns 20% to 80% rise/fall time10-ns propagation delayLow current consumption–40°C to 85°C operating temperature rangeClock frequency range: DC to 24 MHz1.2-V to 1.8-V LVCMOS clock level translation:VDD_IN = 1.2 V ± 10%VDD_OUT = 1.8 V ± 10%Low additive jitter and phase noise:0.8-ps maximum 12-kHz to 5-MHz additive RMS jitter (fout= 24 MHz)–120-dBc/Hz maximum phase noise at 1-kHz offset (fout= 24 MHz)–148-dBc/Hz maximum phase noise floor (fout= 24 MHz, foffset≥ 1 MHz)5-ns 20% to 80% rise/fall time10-ns propagation delayLow current consumption–40°C to 85°C operating temperature range
Description
AI
The CDCBT1001 is a 1.2-V to 1.8-V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ± 10%
The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is less than 0.8 ps.
The CDCBT1001 is a 1.2-V to 1.8-V clock buffer and level translator. The VDD_IN pin supply voltage defines the input LVCMOS clock level. The VDD_OUT pin supply voltage defines the output LVCMOS clock level. VDD_IN = 1.2 V ± 10%. VDD_OUT = 1.8 V ± 10%
The 12-kHz to 5-MHz additive RMS jitter at 24 MHz is less than 0.8 ps.