CD74HC4017-Q1 Series
Automotive Catalog Decade Counter/Divider with 10 Decoded Outputs
Manufacturer: Texas Instruments
Link to Manufacturer Page: https://www.ti.com/
Catalog
Automotive Catalog Decade Counter/Divider with 10 Decoded Outputs
| Part | Timing | Mounting Type | Logic Type | Trigger Type | Grade | Operating Temperature [Min] | Operating Temperature [Max] | Package / Case [x] | Package / Case | Package / Case [x] | Direction | Number of Elements [custom] | Supplier Device Package | Reset | Qualification | Count Rate | Number of Bits per Element | Voltage - Supply [Max] | Voltage - Supply [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HC4017QPWRG4Q1 | Synchronous | Surface Mount | Counter, Decade | Negative, Positive | Automotive | -40 °C | 125 °C | 0.173 " | 16-TSSOP | 4.4 mm | Up | 1 | 16-TSSOP | Asynchronous | AEC-Q100 | 35 MHz | 10 | 6 V | 2 V |
Key Features
• Qualified for Automotive ApplicationsFully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fMAX= 60 MHz at VCC= 5 V,CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsVCCVoltage = 2 V to 6 VHigh Noise Immunity NILor NIH= 30% of VCC, VCC= 5 VQualified for Automotive ApplicationsFully Static OperationBuffered InputsCommon ResetPositive Edge ClockingTypical fMAX= 60 MHz at VCC= 5 V,CL= 15 pF, TA= 25°CFanout (Over Temperature Range)Standard Outputs . . . 10 LSTTL LoadsBus Driver Outputs . . . 15 LSTTL LoadsBalanced Propagation Delay and Transition TimesSignificant Power Reduction Compared to LSTTL Logic ICsVCCVoltage = 2 V to 6 VHigh Noise Immunity NILor NIH= 30% of VCC, VCC= 5 V
Description
AI
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages.CEdisables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.
The CD74HC4017 is a high-speed silicon-gate CMOS 5-stage Johnson counter with ten decoded outputs. Each of the decoded outputs normally is low and sequentially goes high on the low-to-high transition clock period of the ten-clock-period cycle. The carry (TC) output transitions low to high after output 9 goes from high to low, and can be used in conjunction with the clock enable (CE) input to cascade several stages.CEdisables counting when in the high state. A master reset (MR) input also is provided that, when taken high, sets all the decoded outputs, except output 0, to low.
The device can drive up to ten low-power Schottky equivalent loads.