74ABT240 Series

8-ch, 4.5-V to 5.5-V inverters with TTL-compatible CMOS inputs and 3-state outputs

Catalog(6 parts)

Part	Number of Elements▲▼	Logic Type	Voltage - Supply▲▼	Voltage - Supply▲▼	Operating Temperature▲▼	Operating Temperature▲▼	Supplier Device Package	Mounting Type	Number of Bits per Element▲▼	Package / Case	Package / Case▲▼	Package / Case▲▼	Current - Output High, Low▲▼	Output Type	Package / Case▲▼
Texas Instruments SN74ABT240AN Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-PDIP	2 ul	Buffer, Inverting	5.5 V	4.5 V	85 °C	-40 °C	20-PDIP	Through Hole	4 ul	20-DIP	0.007619999814778566 m	0.007619999814778566 m	0.03200000151991844 A, 0.06400000303983688 A	3-State
Texas Instruments SN74ABT240ADW Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SOIC	2 ul	Buffer, Inverting	5.5 V	4.5 V	85 °C	-40 °C	20-SOIC	Surface Mount	4 ul	20-SOIC			0.03200000151991844 A, 0.06400000303983688 A	3-State	0.007493000011891127 m, 0.007499999832361937 m
Texas Instruments SN74ABT240APWR Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-TSSOP	2 ul	Buffer, Inverting	5.5 V	4.5 V	85 °C	-40 °C	20-TSSOP	Surface Mount	4 ul	20-TSSOP	0.004399999976158142 m		0.03200000151991844 A, 0.06400000303983688 A	3-State	0.004394200164824724 m
Texas Instruments SN74ABT240ADBLE Element Bit per Element Output
Texas Instruments SN74ABT240ADBRG4 Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SSOP	2 ul	Buffer, Inverting	5.5 V	4.5 V	85 °C	-40 °C	20-SSOP	Surface Mount	4 ul	20-SSOP			0.03200000151991844 A, 0.06400000303983688 A	3-State	0.0052999998442828655 m, 0.005308600142598152 m
Texas Instruments SN74ABT240ADWR Buffer, Inverting 2 Element 4 Bit per Element 3-State Output 20-SOIC	2 ul	Buffer, Inverting	5.5 V	4.5 V	85 °C	-40 °C	20-SOIC	Surface Mount	4 ul	20-SOIC			0.03200000151991844 A, 0.06400000303983688 A	3-State	0.007493000011891127 m, 0.007499999832361937 m

Key Features

• Typical VOLP(Output Ground Bounce)<1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (–32-mA IOH, 64-mA IOL)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)Typical VOLP(Output Ground Bounce)<1 V at VCC= 5 V, TA= 25°CHigh-Drive Outputs (–32-mA IOH, 64-mA IOL)IoffSupports Partial-Power-Down Mode OperationLatch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17ESD Protection Exceeds JESD 222000-V Human-Body Model (A114-A)200-V Machine Model (A115-A)

Description

These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE)\ inputs, and complementary OE and OE\ inputs. The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE\ inputs. When OE\ is low, the devices pass inverted data from the A inputs to the Y outputs. When OE\ is high, the outputs are in the high-impedance state. This device is fully specified for partial-power-down applications using Ioff. The Ioffcircuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE\ should be tied to VCCthrough a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.