The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-SOIC (0.154", 3.90mm Width)

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-DIP (0.300", 7.62mm)

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

Flip Flop 1 Element D-Type 6 Bit Positive Edge 16-TSSOP (0.173", 4.40mm Width)

The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174. The ’HC174 and ’HCT174 are edge triggered flip-flops which utilize silicon gate CMOS circuitry to implement D-type flip-flops. They possess low power and speeds comparable to low power Schottky TTL circuits. The devices contain six master-slave flip-flops with a common clock and common reset. Data on the D input having the specified setup and hold times is transferred to the Q output on the low to high transition of the CLOCK input. The MR\ input, when low, sets all outputs to a low state. Each output can drive ten low power Schottky TTL equivalent loads. The ’HCT174 is functional as well as, pin compatible to the ’LS174.

The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs. The SNx4HC174 contains six positive-edge-triggered D-type flip-flops with shared clock (CLK) and clear (CLR)inputs.