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TSSOP (PW)

CLVC573AQPWRG4Q1

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Texas Instruments

AUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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TSSOP (PW)

CLVC573AQPWRG4Q1

Active
Texas Instruments

AUTOMOTIVE CATALOG OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

Find alt

Description

General part information

SN74LVC573A-Q1 Series

The SN74LVC573A octal transparent D-type latch is designed for 2.7-V to 3.6-V VCCoperation.

This device features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels at the D inputs.

Technical Specifications

Parameters and characteristics for this part

SpecificationCLVC573AQPWRG4Q1
Circuit8:8
Current - Output High24 mA
Current - Output Low24 mA
Delay Time - Propagation1 ns
GradeAutomotive
Independent Circuits1
Logic TypeD-Type Transparent Latch
Mounting TypeSurface Mount
Operating Temperature (Max)125 °C
Operating Temperature (Min)-40 °C
Output TypeTri-State
Package Length0.173 in
Package Name20-TSSOP
Package Width4.4 mm
QualificationAEC-Q100
Voltage - Supply (Maximum)3.6 V
Voltage - Supply (Minimum)2 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS
16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
How to Select Little Logic (Rev. A)
Use of the CMOS Unbuffered Inverter in Oscillator Circuits
Standard Linear & Logic for PCs, Servers & Motherboards
Understanding Advanced Bus-Interface Products Design Guide
Texas Instruments Little Logic Application Report
LVC Characterization Information
Low-Voltage Logic (LVC) Designer's Guide
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Power-Up Behavior of Clocked Devices (Rev. B)
Octal Transparent D-Type Latch With 3-State Outputs datasheet (Rev. B)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Logic Guide (Rev. AB)
Input and Output Characteristics of Digital Integrated Circuits
Design Summary for WCSP Little Logic (Rev. B)
Automotive Logic Devices Brochure
Selecting the Right Level Translation Solution (Rev. A)
Live Insertion
CMOS Power Consumption and CPD Calculation (Rev. B)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Signal Switch Data Book (Rev. A)
Little Logic Guide 2018 (Rev. G)
Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices
LOGIC Pocket Data Book (Rev. B)