MAX5893EGK+D
Active12-BIT, 500MSPS INTERPOLATING AND MODULATING DUAL DAC WITH CMOS INPUTS
MAX5893EGK+D
Active12-BIT, 500MSPS INTERPOLATING AND MODULATING DUAL DAC WITH CMOS INPUTS
Description
General part information
MAX5893 Series
The MAX5893 programmable interpolating, modulating, 500Msps, dual digital-to-analog converter (DAC) offers superior dynamic performance and is optimized for high-performance wideband, single-carrier transmit applications. The device integrates a selectable 2x/4x/8x interpolating filter, a digital quadrature modulator, and dual 12-bit high-speed DACs on a single integrated circuit. At 30MHz output frequency and 500Msps update rate, the in-band SFDR is 84dBc while consuming 1.1W. The device also delivers 72dB ACLR for single-carrier WCDMA at a 61.44MHz output frequency.The selectable interpolating filters allow lower input data rates while taking advantage of the high DAC update rates. These linear-phase interpolation filters ease reconstruction filter requirements and enhance the passband dynamic performance. Individual offset and gain programmability allow the user to calibrate out local oscillator (LO) feedthrough and sideband suppression errors generated by analog quadrature modulators.The MAX5893 features a fIM/4 digital image-reject modulator. This modulator generates a quadrature-modulated IF signal that can be presented to an analog I/Q modulator to complete the upconversion process. A second digital modulation mode allows the signal to be frequency-translated with image pairs at fIM/2 or fIM/4.The MAX5893 features a standard 1.8V CMOS, 3.3V tolerant data input bus for easy interface. A 3.3V SPI™ port is provided for mode configuration. The programmable modes include the selection of 2x/4x/8x interpolating filters, fIM/2, fIM/4 or no digital quadrature modulation with image rejection, channel gain and offset adjustment, and offset binary or two's complement data interface.Pin-compatible 14- and 16-bit devices are also available. Refer to theMAX5894data sheet for the 14-bit version and theMAX5895data sheet for the 16-bit version.See a parametric table of the complete family of pin-compatible 12-/14-/16-bit high-speed DACs.ApplicationsAnalog Quadrature Modulation ArchitecturesBase Stations: 3G UMTS, CDMA, and GSMBroadband Cable InfrastructureBroadband Wireless TransmittersInstrumentation and Automatic Test Equipment (ATE)
Technical Specifications
Parameters and characteristics for this part
| Specification | MAX5893EGK+D |
|---|---|
| Architecture | Oversampling Interpolating DAC |
| Data Interface | Parallel |
| Differential Output | Yes |
| DNL (LSB) Tolerance | 0.5 LSB |
| INL (LSB) Tolerance | 1 LSB |
| Mounting Type | Surface Mount |
| Number of Bits | 12 bits |
| Number of D/A Converters | 2 count |
| Operating Temperature (Max) | 85 °C |
| Operating Temperature (Min) | -40 °C |
| Output Type | Current - Unbuffered |
| Package / Case | 68-VFQFN Exposed Pad |
| Package Length | 10 mm |
| Package Name | 68-QFN |
| Package Width | 10 mm |
| Reference Type | External, Internal |
| Settling Time (Typical) | 11 ns |
| Voltage - Supply, Analog (Range 1 Max) | 1.89 V |
| Voltage - Supply, Analog (Range 1 Min) | 1.71 V |
| Voltage - Supply, Analog (Range 2 Max) | 3.465 V |
| Voltage - Supply, Analog (Range 2 Min) | 3.135 V |
| Voltage - Supply, Digital (Max) | 1.89 V |
| Voltage - Supply, Digital (Min) | 1.71 V |
Pricing
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