Zenode.ai Logo
270PGILF - 270 - Block Diagram

270PGILF

Active
Renesas Electronics Corporation

TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK

Deep-Dive with AI

Search across all available documentation for this part.

270PGILF - 270 - Block Diagram

270PGILF

Active
Renesas Electronics Corporation

TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

Specification270PGILF
Differential - Input:OutputFalse
Frequency - Max [Max]200 MHz
InputCrystal
Mounting TypeSurface Mount
Number of Circuits1
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
OutputCMOS
Package / Case20-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
PLLYes with Bypass
Ratio - Input:Output1:8
Supplier Device Package20-TSSOP
TypeClock/Frequency Synthesizer, Fanout Buffer (Distribution)
Voltage - Supply [Max]3.465 V
Voltage - Supply [Min]3.135 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$

270 Series

Triple PLL Field Programmable VCXO Clock

PartVoltage - Supply [Max]Voltage - Supply [Min]PLLOperating Temperature [Max]Operating Temperature [Min]InputPackage / Case [y]Package / CasePackage / Case [x]Mounting TypeNumber of CircuitsRatio - Input:OutputFrequency - Max [Max]TypeOutputSupplier Device PackageDifferential - Input:Output
Renesas Electronics Corporation
270PGILF
3.465 V
3.135 V
Yes with Bypass
85 °C
-40 °C
Crystal
4.4 mm
20-TSSOP
0.173 in
Surface Mount
1
1:8
200 MHz
Clock/Frequency Synthesizer, Fanout Buffer (Distribution)
CMOS
20-TSSOP

Description

General part information

270 Series

The 270 field programmable VCXO clock synthesizer generates up to eight high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency crystal input. It is designed to replace crystals and crystal oscillators in most electronic systems. Using IDT's VersaClockTM software to configure PLLs and outputs, the 270 contains a One-Time Programmable (OTP) ROM for field programmability. Programming features include VCXO, eight selectable configuration registers and up to two sets of four low-skew outputs. Using Phase-Locked Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal, or clock. It can replace VCXOs, multiple crystals and oscillators, saving board space and cost. The 270 is also available in factory programmed custom versions for high-volume applications.

Documents

Technical documentation and resources