
MT46V64M8P-5B:J
ActiveDDR DRAM, 64MX8, 0.7NS, CMOS, PDSO66, 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
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MT46V64M8P-5B:J
ActiveDDR DRAM, 64MX8, 0.7NS, CMOS, PDSO66, 0.400 INCH, LEAD FREE, PLASTIC, TSOP-66
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Technical Specifications
Parameters and characteristics for this part
| Specification | MT46V64M8P-5B:J |
|---|---|
| Access Time | 700 ps |
| Clock Frequency | 200 MHz |
| Memory Format | DRAM |
| Memory Interface | Parallel |
| Memory Organization | 64 M |
| Memory Size | 64 MB |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 66-TSSOP |
| Package / Case [custom] | 0.4 in |
| Package / Case [custom] | 0.4 in |
| Supplier Device Package | 66-TSOP |
| Voltage - Supply [Max] | 2.7 V |
| Voltage - Supply [Min] | 2.5 V |
| Write Cycle Time - Word, Page | 15 ns |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 6.01 | |
| 10 | $ 5.48 | |||
| 25 | $ 5.38 | |||
| 40 | $ 5.34 | |||
| 80 | $ 4.79 | |||
| 230 | $ 4.77 | |||
| 440 | $ 4.47 | |||
| 1080 | $ 4.28 | |||
Description
General part information
MT46V64M8 Series
MT46V64M8P-5B:J is a double data rate (DDR) SDRAM. It uses a double data rate architecture to achieve high-speed operation. This double data rate architecture is essentially for 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the memory consists of a single 2n-bit-wide, one-clock cycle data transfer at the internal DRAM core and two corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. It has an internal, pipelined double-data-rate (DDR) architecture with two data accesses per clock cycle.
Documents
Technical documentation and resources
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