M24128-DRDW8TP/K
ActiveEEPROM SERIAL-I2C 128K-BIT 16K X 8 2.5V/3.3V/5V 8-PIN TSSOP T/R
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M24128-DRDW8TP/K
ActiveEEPROM SERIAL-I2C 128K-BIT 16K X 8 2.5V/3.3V/5V 8-PIN TSSOP T/R
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Technical Specifications
Parameters and characteristics for this part
| Specification | M24128-DRDW8TP/K |
|---|---|
| Access Time | 450 ns |
| Grade | Automotive |
| Memory Format | EEPROM |
| Memory Interface | I2C |
| Memory Organization | 16K x 8 |
| Memory Size | 16 kB |
| Memory Type | Non-Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-TSSOP |
| Package / Case [custom] | 0.173 " |
| Package / Case [custom] | 4.4 mm |
| Qualification | AEC-Q100 |
| Supplier Device Package | 8-TSSOP |
| Technology | EEPROM |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.8 V |
| Write Cycle Time - Word, Page | 4 ms |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 0.66 | |
| 10 | $ 0.60 | |||
| 25 | $ 0.60 | |||
| 50 | $ 0.59 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.53 | |||
| 500 | $ 0.52 | |||
| 1000 | $ 0.50 | |||
| Digi-Reel® | 1 | $ 0.66 | ||
| 10 | $ 0.60 | |||
| 25 | $ 0.60 | |||
| 50 | $ 0.59 | |||
| 100 | $ 0.53 | |||
| 250 | $ 0.53 | |||
| 500 | $ 0.52 | |||
| 1000 | $ 0.50 | |||
| Tape & Reel (TR) | 4000 | $ 0.46 | ||
| 8000 | $ 0.45 | |||
| 12000 | $ 0.44 | |||
Description
General part information
M24128-A125 Series
The M24128-A125 is a 128-Kbit serial EEPROM Automotive grade device operating up to 125 °C. The M24128-A125 is compliant with the very high level of reliability defined by the Automotive standard AEC-Q100 grade 1.
The device is accessed by a simple serial I2C compatible interface running up to 1 MHz.
The memory array is based on advanced true EEPROM technology (Electrically Erasable PROgrammable Memory). The M24128-A125 is a byte-alterable memory (16 K × 8 bits) organized as 256 pages of 64 byte in which the data integrity is significantly improved with an embedded Error Correction Code logic.