Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L4P5QGI6TR |
|---|---|
| Connectivity | LINbus, UART/USART, SPI, EBI/EMI, IrDA, I2C, SAI, USB OTG, CANbus, MMC/SD |
| Core Processor | ARM® Cortex®-M4 |
| Core Size | 32-Bit Single-Core |
| Data Converters | A/D 16x12b SAR, D/A 2x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 110 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 132-UFBGA |
| Peripherals | WDT, PWM, LCD, POR, Brown-out Detect/Reset, DMA |
| Program Memory Size | 1 MB |
| Program Memory Type | FLASH |
| RAM Size | 448 K |
| Speed | 120 MHz |
| Supplier Device Package | 132-UFBGA (7x7) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2500 | $ 7.39 | |
Description
General part information
STM32L4P5ZG Series
STM32L4P5xx designates a family of ultra-low-power microcontroller devices (part of STM32L4+ Series) based on the high-performance Arm®Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 120 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm®single-precision data-processing instructions and all the data types. The Cortex-M4 core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application’s security.
These devices embed high-speed memories (up to 1 Mbyte of Flash memory and 320 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), two OCTOSPI Flash memory interfaces (for devices with packages of 100 pins or more) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources