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STM32G484MET6

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STMicroelectronics

MAINSTREAM ARM CORTEX-M4 MCU 170 MHZ WITH 512 KBYTES OF FLASH MEMORY, MATH ACCELERATOR, HR TIMER, HIGH ANALOG LEVEL INTEGRATION, CRYPTO

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STM32G484MET6

Active
STMicroelectronics

MAINSTREAM ARM CORTEX-M4 MCU 170 MHZ WITH 512 KBYTES OF FLASH MEMORY, MATH ACCELERATOR, HR TIMER, HIGH ANALOG LEVEL INTEGRATION, CRYPTO

Deep-Dive with AI

Technical Specifications

Parameters and characteristics for this part

SpecificationSTM32G484MET6
ConnectivityI2C, SAI, SPI, CANbus, UART/USART, LINbus, QSPI, USB, IrDA
Core ProcessorARM® Cortex®-M4
Core Size32-Bit
Data Converters [custom]12, 12
Data Converters [custom]7, 41
Mounting TypeSurface Mount
Number of I/O66 I/O
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Oscillator TypeExternal, Internal
Package / Case80-LQFP
PeripheralsBrown-out Detect/Reset, DMA, POR, WDT, PWM, I2S
Program Memory Size512 KB
Program Memory TypeFLASH
RAM Size128 K
Voltage - Supply (Vcc/Vdd) [Max]3.6 V
Voltage - Supply (Vcc/Vdd) [Min]1.71 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBulk 714$ 5.67

Description

General part information

STM32G484CE Series

The STM32G484xE devices are based on the high-performance Arm®Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz.

The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.

These devices embed high-speed memories (up to 512 Kbytes of flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad-SPI flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.

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Technical documentation and resources

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