ZL30110LDG1
ActiveIC DPLL RATE CONVERSION 32QFN
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ZL30110LDG1
ActiveIC DPLL RATE CONVERSION 32QFN
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Technical Specifications
Parameters and characteristics for this part
| Specification | ZL30110LDG1 |
|---|---|
| Differential - Input:Output | False |
| Input | LVCMOS, Crystal |
| Main Purpose | Telecom |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Output | LVCMOS |
| Package / Case | 32-VFQFN Exposed Pad |
| PLL | True |
| Ratio - Input:Output [custom] | 2:4 |
| Supplier Device Package | 32-QFN (5x5) |
| Voltage - Supply [Max] | 3.5 V |
| Voltage - Supply [Min] | 3.1 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 490 | $ 12.28 | |
| Microchip Direct | TRAY | 1 | $ 15.26 | |
| 25 | $ 12.69 | |||
| 100 | $ 11.54 | |||
| 1000 | $ 10.67 | |||
| 5000 | $ 10.12 | |||
ZL30110 Series
PDH/SDH System Synchronizer
| Part | Input | Voltage - Supply [Min] | Voltage - Supply [Max] | PLL | Output | Supplier Device Package | Package / Case | Mounting Type | Ratio - Input:Output [custom] | Number of Circuits | Differential - Input:Output | Main Purpose | Operating Temperature [Max] | Operating Temperature [Min] |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology ZL30110LDG1 | Crystal, LVCMOS | 3.1 V | 3.5 V | LVCMOS | 32-QFN (5x5) | 32-VFQFN Exposed Pad | Surface Mount | 2:4 | 1 | Telecom | 85 °C | -40 °C |
Description
General part information
ZL30110 Series
The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.
Documents
Technical documentation and resources