Catalog
PDH/SDH System Synchronizer
Key Features
- Synchronizes to 8 kHz, 2.048 MHz, 8.192 MHz or 16.384 MHz
- Provides DPLL lock and reference fail indication
- Automatic free run mode on reference fail
- DPLL bandwidth of 922 Hz for all rates of input reference and 58 Hz for an 8 kHz input reference
- Less than 5 psecrmson 25 MHz outputs, and less than 0.6 nsppintrinsic jitter on the all other outputs
- Minimal input to output and output to output skew
- 25 MHz external master clock source: clock oscillator or crystal
- Simple hardware control interface
•
• Provides a range of output clocks:* 65.536 MHz TDM clock locked to the input reference
• * General purpose 25 MHz fan-out to 6 outputs locked to the external crystal or oscillator
• * General purpose 125 MHz and 66 MHz or 100 MHz locked to the external crystal or oscillator
Description
AI
The ZL30110 clock rate conversion digital phase-locked loop (DPLL) provides accurate and reliable frequency conversion. The ZL30110 generates a range of clocks that are either locked to the input reference or locked to the external crystal or oscillator. In the locked mode, the reference input is continuously monitored for a failure condition. In the event of a failure, the DPLL continues to provide a stable free running clock ensuring system reliability.