Technical Specifications
Parameters and characteristics for this part
| Specification | STM32F410RBT7 |
|---|---|
| Connectivity | LINbus, I2C, IrDA, SPI, UART/USART |
| Core Processor | ARM® Cortex®-M4 |
| Core Size | 32-Bit Single-Core |
| Data Converters | D/A 1x12b, A/D 16x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 50 I/O |
| Operating Temperature [Max] | 105 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 64-LQFP |
| Peripherals | Brown-out Detect/Reset, DMA, POR, WDT, PWM, I2S |
| Program Memory Size | 128 KB |
| Program Memory Type | FLASH |
| Speed | 100 MHz |
| Supplier Device Package | 64-LQFP (10x10) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 6.51 | |
| 10 | $ 4.41 | |||
| 25 | $ 3.86 | |||
| 80 | $ 3.34 | |||
| 230 | $ 2.98 | |||
| 440 | $ 2.81 | |||
| 960 | $ 2.64 | |||
| 2880 | $ 2.45 | |||
Description
General part information
NUCLEO-F410RB Series
The STM32F410x8/B devices are based on the high-performance ARM®Cortex®-M4 32-bit RISC core operating at a frequency of up to 100 MHz. Their Cortex®-M4 core features a Floating point unit (FPU) single precision which supports all ARM single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32F410x8/B belong to the STM32 Dynamic Efficiency™ product line (with products combining power efficiency, performance and integration) while adding a new innovative feature called Batch Acquisition Mode (BAM) allowing to save even more power consumption during data batching.
The STM32F410x8/B incorporate high-speed embedded memories (up to 128 Kbytes of Flash memory, 32 Kbytes of SRAM), and an extensive range of enhanced I/Os and peripherals connected to two APB buses, one AHB bus and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources