S80KS2562GABHI020 is a 256Mb, high-speed CMOS, HYPERRAM™ self-refresh dynamic RAM (DRAM) with HYPERBUS™ interface. DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by HYPERBUS™ interface host. Since host is not required to manage any refresh operations, the DRAM array appears to the host as though memory uses static cells that retain data without refresh. Hence, memory is more accurately described as pseudo static RAM (PSRAM). Since DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The host must confine the duration of transactions and allow additional initial access latency, at the beginning of a new transaction, if the memory indicates a refresh operation is needed.