STM32H563ZIT6
ActiveHIGH-PERFORMANCE, ARM CORTEX-M33 WITH TRUSTZONE, MCU WITH 2-MBYTE FLASH, 640-KBYTE RAM, 250 MHZ CPU
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STM32H563ZIT6
ActiveHIGH-PERFORMANCE, ARM CORTEX-M33 WITH TRUSTZONE, MCU WITH 2-MBYTE FLASH, 640-KBYTE RAM, 250 MHZ CPU
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Technical Specifications
Parameters and characteristics for this part
| Specification | STM32H563ZIT6 |
|---|---|
| Connectivity | I2C, FIFO, SMBus, UART/USART, SPI, CANbus, LINbus, SDIO, IrDA, USB, SCI |
| Core Processor | ARM® Cortex®-M33 |
| Core Size | 32-Bit |
| Data Converters | D/A 2x12b, A/D 18x12b SAR |
| Mounting Type | Surface Mount |
| Number of I/O | 110 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | External, Internal |
| Package / Case | 144-LQFP |
| Peripherals | Voltage Detect, WDT, DMA, Brown-out Detect/Reset, PDR, POR, TRNG, PWM, SHA, I2S |
| Program Memory Size | 2 MB |
| Program Memory Type | FLASH |
| RAM Size | 640 K |
| Speed | 250 MHz |
| Supplier Device Package | 144-LQFP (20x20) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
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Description
General part information
NUCLEO-H563ZI Series
The STM32H562xx and STM32H563xx devices are high-performance microcontrollers of the STM32H5 series, based on the high-performance Arm®Cortex®-M33 32-bit RISC core. They operate at a frequency of up to 250 MHz.
The Cortex®-M33 core features a single-precision floating-point unit (FPU), which supports all the Arm®single-precision data-processing instructions and all the data types. This core implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.
The devices embed high-speed memories (up to 2 Mbytes of dual bank flash memory and 640 Kbytes of SRAM), a flexible external memory controller (FMC) for devices with packages of 100 pins and more, one OCTOSPI memory interface (at least one Quad-SPI available on all packages), and an extensive range of enhanced I/Os and peripherals connected to three APB buses, three AHB buses, and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources