66AK2H12DXAAWA24

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES

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DocumentsPhase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)C66x DSP Cache User's Guide +66

66AK2H12DXAAWA24

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Texas Instruments

HIGH PERFORMANCE MULTICORE DSP+ARM - 4X ARM A15 CORES, 8X C66X DSP CORES

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DocumentsPhase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)C66x DSP Cache User's Guide +66

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	66AK2H12DXAAWA24	66AK2H12 Series

Clock Rate	1.2 GHz, 1.4 GHz	1.2 - 1.4 GHz
Interface	I2C, Serial RapidIO, EBI/EMI, UART/USART, SPI, USB 3.0, Ethernet, DMA	I2C, Serial RapidIO, EBI/EMI, UART/USART, SPI, USB 3.0, Ethernet, DMA
Mounting Type	Surface Mount	Surface Mount
Non-Volatile Memory	384 kB	384 kB
On-Chip RAM	12.75 MB	12.75 MB
Operating Temperature [Max]	100 °C	85 - 100 °C
Operating Temperature [Min]	-40 °C	-40 - 0 °C
Package / Case	FCBGA, 1517-BBGA	FCBGA, 1517-BBGA
Supplier Device Package	1517-FCBGA (40x40)	1517-FCBGA (40x40)
Type	DSP+ARM®	DSP+ARM®
Voltage - Core	Variable	Variable
Voltage - I/O	3.3 V, 0.85 V, 1.5 V, 1.8 V, 1 V, 1.35 V	0.85 - 3.3 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tray	21	$ 922.25
Texas Instruments	JEDEC TRAY (5+1)	1	$ 834.03
		100	$ 754.94
		250	$ 733.37
		1000	$ 718.99

66AK2H12 Series

High performance multicore DSP+Arm - 4x Arm A15 cores, 8x C66x DSP cores

Part	On-Chip RAM	Voltage - Core	Interface	Clock Rate	Package / Case	Operating Temperature [Min]	Operating Temperature [Max]	Supplier Device Package	Voltage - I/O	Type	Mounting Type	Non-Volatile Memory
Texas Instruments 66AK2H12DAAWA24	12.75 MB	Variable	DMA, EBI/EMI, Ethernet, I2C, Serial RapidIO, SPI, UART/USART, USB 3.0	1.2 GHz, 1.4 GHz	1517-BBGA, FCBGA	-40 °C	100 °C	1517-FCBGA (40x40)	0.85 V, 1 V, 1.35 V, 1.5 V, 1.8 V, 3.3 V	DSP+ARM®	Surface Mount	384 kB
Texas Instruments 66AK2H12DAAW24	12.75 MB	Variable	DMA, EBI/EMI, Ethernet, I2C, Serial RapidIO, SPI, UART/USART, USB 3.0	1.2 GHz, 1.4 GHz	1517-BBGA, FCBGA	0 °C	85 °C	1517-FCBGA (40x40)	0.85 V, 1 V, 1.35 V, 1.5 V, 1.8 V, 3.3 V	DSP+ARM®	Surface Mount	384 kB
Texas Instruments 66AK2H12DAAW2	12.75 MB	Variable	DMA, EBI/EMI, Ethernet, I2C, Serial RapidIO, SPI, UART/USART, USB 3.0	1.2 GHz	1517-BBGA, FCBGA	0 °C	85 °C	1517-FCBGA (40x40)	0.85 V, 1 V, 1.35 V, 1.5 V, 1.8 V, 3.3 V	DSP+ARM®	Surface Mount	384 kB
Texas Instruments 66AK2H12DAAWA2	12.75 MB	Variable	DMA, EBI/EMI, Ethernet, I2C, Serial RapidIO, SPI, UART/USART, USB 3.0	1.2 GHz	1517-BBGA, FCBGA	-40 °C	100 °C	1517-FCBGA (40x40)	0.85 V, 1 V, 1.35 V, 1.5 V, 1.8 V, 3.3 V	DSP+ARM®	Surface Mount	384 kB
Texas Instruments 66AK2H12DXAAWA24	12.75 MB	Variable	DMA, EBI/EMI, Ethernet, I2C, Serial RapidIO, SPI, UART/USART, USB 3.0	1.2 GHz, 1.4 GHz	1517-BBGA, FCBGA	-40 °C	100 °C	1517-FCBGA (40x40)	0.85 V, 1 V, 1.35 V, 1.5 V, 1.8 V, 3.3 V	DSP+ARM®	Surface Mount	384 kB

Description

General part information

66AK2H12 Series

The 66AK2Hxx platform combines the quad ARM Cortex-A15 processor with up to eight TMS320C66x high-performance DSPs using the KeyStone II architecture. The 66AK2H14/12/06 device provides up to 5.6 GHz of ARM and 9.6 GHz of DSP processing coupled with security, packet processing, and Ethernet switching at lower power than multichip solutions. The 66AK2H14/12/06 device is optimal for embedded infrastructure applications like cloud computing, media processing, high-performance computing, transcoding, security, gaming, analytics, and virtual desktop.

The C66x core combines fixed-point and floating-point computational capability in the processor without sacrificing speed, size, or power consumption. The raw computational performance is 38.4 GMACS/core and 19.2 Gflops/core (@ 1.2 GHz operating frequency). The C66x is also 100% backward compatible with software for C64x+ devices. The C66x core incorporates 90 new instructions targeted for floating point (FPi) and vector math oriented (VPi) processing.

The 66AK2H14/12/06 device has a complete set of development tools that includes: a C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows®debugger interface for visibility into source code execution.

Documents

Technical documentation and resources

66AK2H12DXAAWA24

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66AK2H12DXAAWA24

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Technical Specifications

Pricing

66AK2H12 Series

Description

66AK2H12 Series

Documents

Phase-Locked Loop (PLL) for KeyStone Devices User's Guide (Rev. I)

C66x DSP Cache User's Guide

Memory Protection Unit (MPU) for KeyStone Devices User's Guide (Rev. A)

Packet Accelerator (PA) for KeyStone Devices User's Guide (Rev. A)

KeyStone™-II-based processors: 10G Ethernet as an optical interface

PCIe Use Cases for KeyStone Devices

General-Purpose Input/Output (GPIO) forKeyStone Devices User's Guide

DDR3 Memory Controller for KeyStone II Devices User's Guide (Rev. C)

Implementing an FTP Server on TI 66AK2H Device With RTOS

Keystone EDMA FAQ

How to Migrate CCS 3.x Projects to the Latest CCS (Rev. A)

Thermal Design Guide for DSP and Arm Application Processors (Rev. B)

Power Consumption Summary for 66AK2Hx System-on-Chip (SoC) Device Family

Multicore SoCs stay a step ahead of SoC FPGAs

Security Accelerator (SA) for KeyStone Devices User's Guide (Rev. B)

PCI Express (PCIe) for KeyStone Devices User's Guide (Rev. D)

Optimizing Loops on the C66x DSP

Hardware Design Guide for KeyStone II Devices

Power Sleep Controller (PSC) for KeyStone Devices User's Guide (Rev. C)

Clocking Design Guide for KeyStone Devices

KeyStone II DDR3 interface bring-up

Keystone Error Detection and Correction EDC ECC (Rev. A)

Multicore Navigator (CPPI) for KeyStone Architecture User's Guide (Rev. H)

Throughput Performance Guide for KeyStone II Devices (Rev. B)

C66x CorePac User's Guide (Rev. C)

TI DSP Benchmarking

Gigabit Ethernet Switch Subsystem for KeyStone Devices User's Guide (Rev. D)

External Memory Interface (EMIF16) for KeyStone Devices User's Guide (Rev. A)

C66x CPU and Instruction Set Reference Guide

DSP Bootloader for KeyStone Architecture User's Guide (Rev. C)

DDR3 Design Requirements for KeyStone Devices (Rev. D)

ARM Optimizing C/C++ Compiler v5.2 User's Guide (Rev. J)

66AK2Hx KeyStone Multicore DSP+ARM System-on-chips (Rev. A)

ARM Assembly Language Tools v5.2 User's Guide (Rev. M)

Keystone II DDR3 Debug Guide

Chip Interrupt Controller (CIC) for KeyStone Devices User's Guide (Rev. A)

ARM CorePac User Guide for KeyStone II Devices

Power Management of KS2 Device (Rev. C)

Introduction to HVDC Architecture and Solutions for Control and Protection (Rev. B)

Multicore Programming Guide (Rev. B)

Software and Hardware Design Challenges Due to Dynamic Raw NAND Market

Serial Peripheral Interface (SPI) for KeyStone Devices User’s Guide (Rev. A)

Network Coprocessor for KeyStone Devices User's Guide

66AK2Hxx Multicore DSP+ARM KeyStone II SOC Errata (Revs 1.0, 1.1, 2.0, 3.0, 3.1) (Rev. F)

Keystone Multicore Device Family Schematic Checklist

Multicore DSPs for High-Performance Video Coding

ARM Bootloader User Guide for KeyStone II Devices

64-Bit Timer (Timer64) for KeyStone Devices User's Guide (Rev. A)

TI’s processors leading the way in embedded analytics

Inter-Integrated Circuit (I2C) for KeyStone Devices User's Guide

Serializer/Deserializer (SerDes) for KeyStone II Devices User Guide (Rev. A)

Multicore Shared Memory Controller (MSMC) User Guide for KeyStone II Devices

Introduction to TMS320C6000 DSP Optimization

66AK2Hxx Multicore DSP+ARM® KeyStone II System-on-Chip (SoC) datasheet (Rev. G)

Universal Asynchronous Receiver/Transmitter (UART) for KeyStone Devices UG

Using DSPLIB FFT Implementation for Real Input and Without Data Scaling

KeyStone II Architecture Universal Serial Bus 3.0 (USB 3.0) (Rev. A)

Using Arm ROM Bootloader on Keystone II Devices

HyperLink for KeyStone Devices User's Guide (Rev. C)

Industrial Imaging: Applications of the K2H and K2E platforms

Keystone NDK FAQ

SERDES Link Commissioning on KeyStone I and II Devices

Video Infrastructure - Applications of the K2E, K2H platforms

Serial RapidIO (SRIO) for KeyStone Devices User's Guide (Rev. C)

Enhanced Direct memory Access 3 (EDMA3) for KeyStone Devices User's Guide (Rev. B)

Keystone II DDR3 Initialization

Debug and Trace for KeyStone II Devices User's Guide

Datasheet