Zenode.ai Logo
SN74LVC126APW - https://ti.com/content/dam/ticom/images/products/package/p/pw0014a.png

SN74LVC126APW

Active
Texas Instruments

FOUR-CHANNEL, 1.65V TO 3.6V BUFFERS WITH THREE-STATE OUTPUTS

Deep-Dive with AI

Search across all available documentation for this part.

SN74LVC126APW - https://ti.com/content/dam/ticom/images/products/package/p/pw0014a.png

SN74LVC126APW

Active
Texas Instruments

FOUR-CHANNEL, 1.65V TO 3.6V BUFFERS WITH THREE-STATE OUTPUTS

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationSN74LVC126APW74LVC126 Series
Current - Output High, Low [custom]24 mA24 mA
Current - Output High, Low [custom]24 mA24 mA
Grade-Automotive
Logic TypeBuffer, Non-InvertingBuffer, Non-Inverting
Mounting TypeSurface MountSurface Mount
Number of Bits per Element11
Number of Elements44
Operating Temperature [Max]125 °C85 - 125 °C
Operating Temperature [Min]-40 °C-40 °C
Output Type3-State3-State
Package / Case14-TSSOP14-TSSOP, 14-VFQFN Exposed Pad, 14-SOIC, 14-SSOP, 14-TFSOP
Package / Case-3.9 mm
Package / Case-0.154 - 5.3 in
Package / Case-5.3 mm
Package / Case-0.209 in
Package / Case-0.209 - 4.4 in
Package / Case [custom]0.173 in0.173 in
Package / Case [custom]4.4 mm4.4 mm
Qualification-AEC-Q100
Supplier Device Package14-TSSOP14-TSSOP, 14-VQFN (3.5x3.5), 14-SO, 14-SSOP
Voltage - Supply [Max]3.6 V3.6 V
Voltage - Supply [Min]1.65 V1.65 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

74LVC126 Series

Four-channel, 1.65V to 3.6V buffers with three-state outputs

PartQualificationMounting TypeLogic TypeOutput TypeNumber of Bits per ElementSupplier Device PackageVoltage - Supply [Max]Voltage - Supply [Min]Operating Temperature [Min]Operating Temperature [Max]GradePackage / CasePackage / Case [custom]Package / Case [custom]Current - Output High, Low [custom]Current - Output High, Low [custom]Number of ElementsPackage / CasePackage / CasePackage / Case [y]Package / Case [y]Package / Case
Texas Instruments
SN74LVC126AQPWRQ1
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP
AEC-Q100
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
Automotive
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4
Texas Instruments
SN74LVC126APWT
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4
Texas Instruments
SN74LVC126ARGYRG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-VQFN (3.5x3.5)
Surface Mount
Buffer, Non-Inverting
3-State
1
14-VQFN (3.5x3.5)
3.6 V
1.65 V
-40 °C
85 °C
14-VFQFN Exposed Pad
24 mA
24 mA
4
Texas Instruments
SN74LVC126ADG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ANSR
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
14-SO
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
5.3 mm
0.209 in
Texas Instruments
SN74LVC126ADRG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ADBR
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
14-SSOP
3.6 V
1.65 V
-40 °C
125 °C
14-SSOP
24 mA
24 mA
4
5.3 mm
0.209 in
Texas Instruments
SN74LVC126ADE4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ADTG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ARGYR
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
14-VQFN (3.5x3.5)
3.6 V
1.65 V
-40 °C
85 °C
14-VFQFN Exposed Pad
24 mA
24 mA
4
Texas Instruments
SN74LVC126AQDRQ1
This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation. This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.
AEC-Q100
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
Automotive
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126AD
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ADRE4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SOIC
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126APW
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4
Texas Instruments
SN74LVC126ADT
The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment. The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation. The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Inputs can be driven from either 3.3V or 5V devices. This feature allows the use of this device as a translator in a mixed 3.3V and 5V system environment.
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126ADGVRE4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TVSOP
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
14-TFSOP
24 mA
24 mA
4
4.4 mm
Texas Instruments
SN74LVC126ANS
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-SO
Surface Mount
Buffer, Non-Inverting
3-State
1
14-SO
3.6 V
1.65 V
-40 °C
125 °C
14-SOIC
24 mA
24 mA
4
5.3 mm
0.209 in
Texas Instruments
SN74LVC126AQDRG4Q1
This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation. This quadruple bus buffer gate is designed for 1.65V to 3.6V VCC operation.
AEC-Q100
Surface Mount
Buffer, Non-Inverting
3-State
1
3.6 V
1.65 V
-40 °C
125 °C
Automotive
14-SOIC
24 mA
24 mA
4
3.9 mm
0.154 in
Texas Instruments
SN74LVC126APWRG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4
Texas Instruments
SN74LVC126APWRE4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4
Texas Instruments
SN74LVC126APWG4
Buffer, Non-Inverting 4 Element 1 Bit per Element 3-State Output 14-TSSOP
Surface Mount
Buffer, Non-Inverting
3-State
1
14-TSSOP
3.6 V
1.65 V
-40 °C
125 °C
14-TSSOP
0.173 in
4.4 mm
24 mA
24 mA
4

Description

General part information

74LVC126 Series

The SN74LVC126A device is a quadruple bus buffer gate designed for 1.65V to 3.6V VCC operation.

The SN74LVC126A device features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE must be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

Documents

Technical documentation and resources

Texas Instruments Little Logic Application Report

Application note

Use of the CMOS Unbuffered Inverter in Oscillator Circuits

Application note

Standard Linear & Logic for PCs, Servers & Motherboards

More literature

Implications of Slow or Floating CMOS Inputs (Rev. E)

Application note

Signal Switch Data Book (Rev. A)

User guide

Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices

Application note

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

Application note

Design Summary for WCSP Little Logic (Rev. B)

Product overview

Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)

Application note

Live Insertion

Application note

TI IBIS File Creation, Validation, and Distribution Processes

Application note

Little Logic Guide 2018 (Rev. G)

Selection guide

Selecting the Right Level Translation Solution (Rev. A)

Application note

How to Select Little Logic (Rev. A)

Application note

18-V/400-W 98% Efficient Compact Brushless DC Motor Drive Design Guide

Design guide

CMOS Power Consumption and CPD Calculation (Rev. B)

Application note

Logic Guide (Rev. AB)

Selection guide

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

SN74LVC126A Quadruple Bus Buffer Gate With 3-State Outputs datasheet (Rev. U)

Data sheet

LOGIC Pocket Data Book (Rev. B)

User guide

Low-Voltage Logic (LVC) Designer's Guide

Design guide

LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B)

User guide

STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS

More literature

Understanding Advanced Bus-Interface Products Design Guide

Application note

Input and Output Characteristics of Digital Integrated Circuits

Application note

LVC Characterization Information

Application note

Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices

Application note

16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)

Application note