SN74AHC00MPWREP
ActiveTexas Instruments
ENHANCED PRODUCT 4-CH, 2-INPUT, 2-V TO 5.5-V NAND GATES
SN74AHC00MPWREP
ActiveTexas Instruments
ENHANCED PRODUCT 4-CH, 2-INPUT, 2-V TO 5.5-V NAND GATES
Description
General part information
74AHC00 Series
The SN74AHC00 device performs the Boolean function Y = A • B or Y = A + B in positive logic.
The SN74AHC00 device performs the Boolean function Y = A • B or Y = A + B in positive logic.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHC00MPWREP |
|---|---|
| Current - Output High | 8 mA |
| Current - Output Low | 8 mA |
| Current - Quiescent (Max) | 2 µA |
| Input Logic Level - High (Max) | 3.85 V |
| Input Logic Level - High (Min) | 1.5 V |
| Input Logic Level - Low (Max) | 1.65 V |
| Input Logic Level - Low (Min) | 0.5 V |
| Logic Type | NAND Gate |
| Max CL | 50 pF |
| Max Propagation Delay | 7.5 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 4 |
| Number of Inputs | 2 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -55 °C |
| Package Length | 0.173 in |
| Package Name | 14-TSSOP |
| Package Width | 4.4 mm |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 2 V |
Pricing
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CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
CMOS Power Consumption and CPD Calculation (Rev. B)
Live Insertion
LOGIC Pocket Data Book (Rev. B)
Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Selecting the Right Level Translation Solution (Rev. A)
Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)
How to Select Little Logic (Rev. A)
Design Summary for WCSP Little Logic (Rev. B)
Quadruple 2-Input Positive-NAND Gate datasheet
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Logic Guide (Rev. AB)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Texas Instruments Little Logic Application Report
AHC/AHCT Designer's Guide February 2000 (Rev. D)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Implications of Slow or Floating CMOS Inputs (Rev. E)
Little Logic Guide 2018 (Rev. G)
Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)
TI IBIS File Creation, Validation, and Distribution Processes
