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CDCUN1208LPEVM - CDCUN1208LPEVM

CDCUN1208LPEVM

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Texas Instruments

EVAL MODULE FOR CDCUN1208LP

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CDCUN1208LPEVM - CDCUN1208LPEVM

CDCUN1208LPEVM

Active
Texas Instruments

EVAL MODULE FOR CDCUN1208LP

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationCDCUN1208LPEVMCDCUN1208 Series
Differential - Input:Output-True
Differential - Input:Output-True
Frequency - Max-400 MHz
FunctionClock BufferClock Buffer
Input-LVDS, HCSL, LVCMOS
Mounting Type-Surface Mount
Number of Circuits-1
Operating Temperature--40 °C
Operating Temperature-85 °C
Output-HCSL, LVCMOS, LVDS
Package / Case-32-VFQFN Exposed Pad
Primary AttributesUSB Powered, External SupplyUSB Powered, External Supply
Ratio - Input:Output-2
Ratio - Input:Output-8
Secondary AttributesSPI/USB InterfacesSPI/USB Interfaces
Supplied ContentsBoard(s)Board(s)
Supplier Device Package-32-VQFN (5x5)
TypeTimingDivider, Fanout Buffer (Distribution), Multiplexer, Timing
Utilized IC / PartCDCUN1208LPCDCUN1208LP
Voltage - Supply-1.7 V
Voltage - Supply-3.63 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyBox 1$ 238.80

CDCUN1208 Series

Ultra-low power, 2:8 fan-out buffer with universal inputs and outputs

PartSupplier Device PackageInputTypeOperating Temperature [Min]Operating Temperature [Max]Differential - Input:Output [custom]Differential - Input:Output [custom]Mounting TypePackage / CaseNumber of CircuitsOutputVoltage - Supply [Min]Voltage - Supply [Max]Frequency - Max [Max]Ratio - Input:Output [custom]Ratio - Input:Output [custom]Primary AttributesFunctionSupplied ContentsUtilized IC / PartSecondary Attributes
Texas Instruments
CDCUN1208LPRHBR
32-VQFN (5x5)
HCSL, LVCMOS, LVDS
Divider, Fanout Buffer (Distribution), Multiplexer
-40 °C
85 °C
Surface Mount
32-VFQFN Exposed Pad
1
HCSL, LVCMOS, LVDS
1.7 V
3.63 V
400 MHz
2
8
Texas Instruments
CDCUN1208LPEVM
Timing
External Supply, USB Powered
Clock Buffer
Board(s)
CDCUN1208LP
SPI/USB Interfaces
Texas Instruments
CDCUN1208LPRHBT
32-VQFN (5x5)
HCSL, LVCMOS, LVDS
Divider, Fanout Buffer (Distribution), Multiplexer
-40 °C
85 °C
Surface Mount
32-VFQFN Exposed Pad
1
HCSL, LVCMOS, LVDS
1.7 V
3.63 V
400 MHz
2
8

Description

General part information

CDCUN1208 Series

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.

The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential/single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge-rate control. The clock buffer supports PCIe Gen1, Gen2 and Gen3. One of the device inputs includes a divider that provides divide values of /1, /2, /4, or /8. The CDCUN1208LP is offered in a 32-pin QFN package, reducing the solution footprint. The device is flexible and easy to use. The state of certain pins determines device configuration at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The output section includes four dedicated supply pins enabling the operation of output ports from different power supply domains. This provides the ability to clock devices switching at different LVCMOS levels without the need for external logic level translation circuitry.

Documents

Technical documentation and resources