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ZL30119GGG2 - 100-CABGA

ZL30119GGG2

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Microchip Technology

SONET/SDH SYSTEM SYNCHRONIZER

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ZL30119GGG2 - 100-CABGA

ZL30119GGG2

Active
Microchip Technology

SONET/SDH SYSTEM SYNCHRONIZER

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Technical Specifications

Parameters and characteristics commom to parts in this series

SpecificationZL30119GGG2ZL30119 Series
Differential - Input:OutputNo/YesNo/Yes
Frequency - Max [Max]622.08 MHz622.08 MHz
InputLVCMOSLVCMOS
Main PurposeTelecom, SONET/SDHTelecom, SONET/SDH
Mounting TypeSurface MountSurface Mount
Number of Circuits11
Operating Temperature [Max]85 °C85 °C
Operating Temperature [Min]-40 °C-40 °C
OutputLVPECL, LVCMOSLVPECL, LVCMOS
Package / Case100-FBGA100-FBGA
PLLTrueTrue
Ratio - Input:Output [custom]1111
Ratio - Input:Output [custom]1414
Supplier Device Package100-CABGA (9x9)100-CABGA (9x9)
Voltage - Supply [Max]3.63 V3.63 V
Voltage - Supply [Min]2.97 V2.97 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 99.01
25$ 82.50
100$ 72.46
Microchip DirectTRAY 1$ 99.01
25$ 82.50
100$ 75.02
1000$ 69.31
5000$ 65.74

ZL30119 Series

IC SONET/SDH SYNCH 100CABGA

PartInputSupplier Device PackageRatio - Input:Output [custom]Ratio - Input:Output [custom]Frequency - Max [Max]Package / CaseOutputNumber of CircuitsPLLDifferential - Input:OutputMounting TypeOperating Temperature [Max]Operating Temperature [Min]Voltage - Supply [Min]Voltage - Supply [Max]Main Purpose
Microchip Technology
ZL30119GGG
LVCMOS
100-CABGA (9x9)
11
14
622.08 MHz
100-FBGA
LVCMOS, LVPECL
1
No/Yes
Surface Mount
85 °C
-40 °C
2.97 V
3.63 V
SONET/SDH, Telecom
Microchip Technology
ZL30119GGG2
LVCMOS
100-CABGA (9x9)
11
14
622.08 MHz
100-FBGA
LVCMOS, LVPECL
1
No/Yes
Surface Mount
85 °C
-40 °C
2.97 V
3.63 V
SONET/SDH, Telecom

Description

General part information

ZL30119 Series

The ZL30119 SONET/SDH Line Card Synchronizer is a highly integrated device that provides timing and synchronization for network interface cards. It incorporates two independent DPLLs, each capable of locking to one of eight input references and provides a wide variety of synchronized output clocks and frame pulses.

Documents

Technical documentation and resources