
LTC2264CUJ-14#TRPBF
Active14-BIT, 40MSPS LOW POWER DUAL ADCS
Deep-Dive with AI
Search across all available documentation for this part.

LTC2264CUJ-14#TRPBF
Active14-BIT, 40MSPS LOW POWER DUAL ADCS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | LTC2264CUJ-14#TRPBF |
|---|---|
| Architecture | Pipelined |
| Configuration | S/H-ADC |
| Data Interface | LVDS - Serial |
| Features | Simultaneous Sampling |
| Input Type | Differential |
| Mounting Type | Surface Mount |
| Number of A/D Converters | 2 |
| Number of Bits | 14 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 70 °C |
| Operating Temperature [Min] | 0 °C |
| Package / Case | 40-WFQFN Exposed Pad |
| Ratio - S/H:ADC | 1:1 |
| Reference Type | External, Internal |
| Sampling Rate (Per Second) | 40M |
| Supplier Device Package | 40-QFN (6x6) |
| Voltage - Supply, Analog [Max] | 1.9 V |
| Voltage - Supply, Analog [Min] | 1.7 V |
| Voltage - Supply, Digital [Max] | 1.9 V |
| Voltage - Supply, Digital [Min] | 1.7 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 2000 | $ 43.08 | |
Description
General part information
LTC2264-14 Series
The LTC2265-14/LTC2264-14/LTC2263-14 are 2-channel, simultaneous sampling 14-bit A/D converters designed for digitizing high frequency, wide dynamic range signals. They are perfect for demanding communications applications with AC performance that includes 73.7dB SNR and 90dB spurious free dynamic range (SFDR). Ultralow jitter of 0.15psRMSallows undersampling of IF frequencies with excellent noise performance.DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) and no missing codes over temperature. The transition noise is a low 1.2LSBRMS.The digital outputs are serial LVDS to minimize the number of data lines. Each channel outputs two bits at a time (2-lane mode) or one bit at a time (1-lane mode). The LVDS drivers have optional internal termination and adjustable output levels to ensure clean signal integrity.The ENC+and ENC–inputs may be driven differentially or single-ended with a sine wave, PECL, LVDS, TTL, or CMOS inputs. An internal clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles.BitsLTC2264-1212LTC2264-1414ApplicationsCommunicationsCellular Base StationsSoftware Defined RadiosPortable Medical ImagingMultichannel Data AcquisitionNondestructive Testing
Documents
Technical documentation and resources