CD74HC190E

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Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER

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Search across all available documentation for this part.

DocumentsCD54HC190, CD74HC190, CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 datasheet (Rev. E)

CD74HC190E

Active

Texas Instruments

HIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS BCD DECADE UP/DOWN COUNTER

Deep-Dive with AI

DocumentsCD54HC190, CD74HC190, CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 datasheet (Rev. E)

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CD74HC190E	74HC190 Series

Count Rate	35 MHz	35 MHz
Direction	Down, Up	Down, Up
Logic Type	Decade, Counter	Decade, Counter
Mounting Type	Through Hole	Surface Mount, Through Hole
Number of Bits per Element	4	4
Number of Elements [custom]	1	1
Operating Temperature [Max]	125 °C	125 °C
Operating Temperature [Min]	-55 °C	-55 °C
Package / Case	0.3 in, 7.62 mm	0.3 - 7.62 in
Package / Case	16-DIP	16-TSSOP, 16-DIP, 16-SOIC (0.209", 5.30mm Width)
Package / Case	-	0.173 "
Package / Case	-	4.4 mm
Supplier Device Package	16-PDIP	16-TSSOP, 16-PDIP, 16-SO
Timing	Synchronous	Synchronous
Trigger Type	Positive Edge	Positive Edge
Voltage - Supply [Max]	6 V	6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.53
		10	$ 1.37
		25	$ 1.29
		100	$ 1.10
		250	$ 1.03
		500	$ 0.90
		1000	$ 0.75
		2500	$ 0.70
		5000	$ 0.67
Texas Instruments	TUBE	1	$ 1.46
		100	$ 1.12
		250	$ 0.82
		1000	$ 0.59

74HC190 Series

High Speed CMOS Logic Presettable Synchronous BCD Decade Up/Down Counter

Part	Trigger Type	Logic Type	Voltage - Supply [Max]	Voltage - Supply [Min]	Timing	Supplier Device Package	Count Rate	Number of Elements [custom]	Package / Case [x]	Package / Case	Package / Case [x]	Mounting Type	Direction	Number of Bits per Element	Operating Temperature [Min]	Operating Temperature [Max]	Package / Case
Texas Instruments CD74HC190PWT Counter IC Counter, Decade 1 Element 4 Bit Positive Edge 16-TSSOP	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-TSSOP	35 MHz	1	0.173 "	16-TSSOP	4.4 mm	Surface Mount	Down, Up	4	-55 °C	125 °C
Texas Instruments CD74HC190E The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-PDIP	35 MHz	1		16-DIP		Through Hole	Down, Up	4	-55 °C	125 °C	0.3 in, 7.62 mm
Texas Instruments CD74HC190PW The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-TSSOP	35 MHz	1	0.173 "	16-TSSOP	4.4 mm	Surface Mount	Down, Up	4	-55 °C	125 °C
Texas Instruments CD74HC190PWR The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3). The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters. Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock. When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2). If a decade counter is preset to an illegal state or assumes an illegal state when power is applied, it returns to the normal sequence in one or two counts, as shown in the state diagrams (see Figure 3).	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-TSSOP	35 MHz	1	0.173 "	16-TSSOP	4.4 mm	Surface Mount	Down, Up	4	-55 °C	125 °C
Texas Instruments CD74HC190NS Counter IC Counter, Decade 1 Element 4 Bit Positive Edge 16-SO	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-SO	35 MHz	1		16-SOIC (0.209", 5.30mm Width)		Surface Mount	Down, Up	4	-55 °C	125 °C
Texas Instruments CD74HC190EG4 Counter IC Counter, Decade 1 Element 4 Bit Positive Edge 16-PDIP	Positive Edge	Counter, Decade	6 V	2 V	Synchronous	16-PDIP	35 MHz	1		16-DIP		Through Hole	Down, Up	4	-55 °C	125 °C	0.3 in, 7.62 mm

Description

General part information

74HC190 Series

The CD54/74HC190 are asynchronously presettable BCD decade counters, whereas the CD54/74HC191 and CD54/74HCT191 are asynchronously presettable binary counters.

Presetting the counter to the number on preset data inputs (A–D) is accomplished by a low asynchronous parallel load (LOAD)\ input. Counting occurs when LOAD\ is high, count enable (CTEN)\ is low, and the down/up (D/U) input is either high for down counting or low for up counting. The counter is decremented or incremented synchronously with the low-to-high transition of the clock.

When an overflow or underflow of the counter occurs, the MAX/MIN output, which is low during counting, goes high and remains high for one clock cycle. This output can be used for look-ahead carry in high-speed cascading (see Figure 1). The MAX/MIN output also initiates the ripple clock (RCO)\ output, which is normally high, goes low and remains low for the low-level portion of the clock pulse. These counters can be cascaded using RCO\ (see Figure 2).

Documents

Technical documentation and resources

CD54HC190, CD74HC190, CD54HC191, CD74HC191, CD54HCT191, CD74HCT191 datasheet (Rev. E)

Data sheet