Zenode.ai Logo
Beta
K
S80KS2564GACHI040 - 49-VBGA

S80KS2564GACHI040

Active
Infineon Technologies

DRAM, DDR, 256 MBIT, 16M X 16BIT, 200 MHZ, FBGA, 49 PINS

Deep-Dive with AI

Search across all available documentation for this part.

DocumentsDatasheet
S80KS2564GACHI040 - 49-VBGA

S80KS2564GACHI040

Active
Infineon Technologies

DRAM, DDR, 256 MBIT, 16M X 16BIT, 200 MHZ, FBGA, 49 PINS

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

SpecificationS80KS2564GACHI040
Access Time35 ns
Clock Frequency200 MHz
Memory FormatPSRAM
Memory InterfaceHyperBus
Memory Organization16 M
Memory Size256 Gbit
Memory TypeVolatile
Mounting TypeSurface Mount
Operating Temperature [Max]85 °C
Operating Temperature [Min]-40 °C
Package / Case49-VBGA
Supplier Device Package49-FBGA (8x8)
TechnologyPSRAM (Pseudo SRAM)
Voltage - Supply [Max]2 V
Voltage - Supply [Min]1.7 V
Write Cycle Time - Word, Page35 ns

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyTray 1$ 6.96
10$ 6.40
25$ 6.27
40$ 6.25
80$ 5.60
260$ 5.43
520$ 5.17
1040$ 4.99
NewarkEach 1$ 7.65
10$ 6.98
25$ 6.69
50$ 6.40
100$ 6.10
250$ 6.09
520$ 6.07

Description

General part information

S80KS2564 Series

S80KS2564GACHI040 is a 256Mb HYPERRAM™ self-refresh DRAM (PSRAM). The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ extended-IO host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed.

Documents

Technical documentation and resources