
S80KS2564GACHI040
ActiveDRAM, DDR, 256 MBIT, 16M X 16BIT, 200 MHZ, FBGA, 49 PINS
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S80KS2564GACHI040
ActiveDRAM, DDR, 256 MBIT, 16M X 16BIT, 200 MHZ, FBGA, 49 PINS
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Technical Specifications
Parameters and characteristics for this part
| Specification | S80KS2564GACHI040 |
|---|---|
| Access Time | 35 ns |
| Clock Frequency | 200 MHz |
| Memory Format | PSRAM |
| Memory Interface | HyperBus |
| Memory Organization | 16 M |
| Memory Size | 256 Gbit |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 49-VBGA |
| Supplier Device Package | 49-FBGA (8x8) |
| Technology | PSRAM (Pseudo SRAM) |
| Voltage - Supply [Max] | 2 V |
| Voltage - Supply [Min] | 1.7 V |
| Write Cycle Time - Word, Page | 35 ns |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
S80KS2564 Series
S80KS2564GACHI040 is a 256Mb HYPERRAM™ self-refresh DRAM (PSRAM). The DRAM array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh operations on the DRAM array when the memory is not being actively read or written by the HYPERBUS™ extended-IO host. Since the host is not required to manage any refresh operations, the DRAM array appears to the host as though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately described as pseudo static RAM (PSRAM). Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed.
Documents
Technical documentation and resources