CD74HC573M96

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HIGH SPEED CMOS LOGIC OCTAL TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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DocumentsInput and Output Characteristics of Digital Integrated Circuits CMOS Power Consumption and CPD Calculation (Rev. B)+13

CD74HC573M96

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Texas Instruments

HIGH SPEED CMOS LOGIC OCTAL TRANSPARENT LATCHES WITH 3-STATE OUTPUTS

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DocumentsInput and Output Characteristics of Digital Integrated Circuits CMOS Power Consumption and CPD Calculation (Rev. B)+13

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CD74HC573M96	74HC573 Series

Circuit	8:8	8:8, 1:8
Current - Output High, Low	7.8 mA, 7.8 mA	7.8 mA
Delay Time - Propagation	30 ns	23 - 30 ns
Grade	-	Automotive
Independent Circuits	1	1
Logic Type	D-Type Transparent Latch	D-Type Transparent Latch
Mounting Type	Surface Mount	Surface Mount, Through Hole
Operating Temperature [Max]	125 °C	85 - 125 °C
Operating Temperature [Min]	-55 °C	-55 - -40 °C
Output Type	Tri-State	Tri-State
Package / Case	7.5 mm, 0.295 in	0.173 - 7.5 in
Package / Case	20-SOIC	20-TSSOP, 20-DIP, 20-SSOP, 20-SOIC
Package / Case	-	0.3 - 4.4 mm
Package / Case	-	7.62 mm
Qualification	-	AEC-Q100
Supplier Device Package	20-SOIC	20-TSSOP, 20-PDIP, 20-SSOP, 20-SOIC, 20-SO
Voltage - Supply [Max]	6 V	6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Cut Tape (CT)	1	$ 0.78
		10	$ 0.69
		25	$ 0.64
		100	$ 0.53
		250	$ 0.49
		500	$ 0.42
		1000	$ 0.33
	Digi-Reel®	1	$ 0.78
		10	$ 0.69
		25	$ 0.64
		100	$ 0.53
		250	$ 0.49
		500	$ 0.42
		1000	$ 0.33
	Tape & Reel (TR)	2000	$ 0.30
		6000	$ 0.28
		10000	$ 0.27
Texas Instruments	LARGE T&R	1	$ 0.56
		100	$ 0.43
		250	$ 0.32
		1000	$ 0.23

74HC573 Series

Octal Transparent D-Type Latches With 3-State Outputs

Part	Package / Case	Package / Case	Package / Case	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Logic Type	Supplier Device Package	Voltage - Supply [Min]	Voltage - Supply [Max]	Current - Output High, Low	Grade	Output Type	Delay Time - Propagation	Qualification	Circuit	Independent Circuits	Package / Case
Texas Instruments SN74HC573AQPWRQ1 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP	0.173 in	4.4 mm	20-TSSOP	Surface Mount	125 °C	-40 °C	D-Type Transparent Latch	20-TSSOP	2 V	6 V	7.8 mA, 7.8 mA	Automotive	Tri-State	23 ns	AEC-Q100	8:8	1
Texas Instruments SN74HC573ANG4 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP		0.3 in	20-DIP	Through Hole	85 °C	-40 °C	D-Type Transparent Latch	20-PDIP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1	7.62 mm
Texas Instruments SN74HC573AQPWRG4Q1 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-TSSOP	0.173 in	4.4 mm	20-TSSOP	Surface Mount	125 °C	-40 °C	D-Type Transparent Latch	20-TSSOP	2 V	6 V	7.8 mA, 7.8 mA	Automotive	Tri-State	23 ns	AEC-Q100	8:8	1
Texas Instruments SN74HC573ADBR The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.	0.209 in, 5.3 mm		20-SSOP	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SSOP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments CD74HC573EG4 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP		0.3 in	20-DIP	Through Hole	125 °C	-55 °C	D-Type Transparent Latch	20-PDIP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	30 ns		8:8	1	7.62 mm
Texas Instruments CD74HC573M D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	125 °C	-55 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	30 ns		8:8	1
Texas Instruments SN74HC573ADWG4 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments SN74HC573BPWR D-Type Transparent Latch 1 Channel 1:8 IC Tri-State 20-TSSOP	0.173 in	4.4 mm	20-TSSOP	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-TSSOP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		1:8	1
Texas Instruments CD74HC573E D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-PDIP		0.3 in	20-DIP	Through Hole	125 °C	-55 °C	D-Type Transparent Latch	20-PDIP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	30 ns		8:8	1	7.62 mm
Texas Instruments SN74HC573AQDWRQ1 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	125 °C	-40 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA	Automotive	Tri-State	23 ns	AEC-Q100	8:8	1
Texas Instruments SN74HC573APWT The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.	0.173 in	4.4 mm	20-TSSOP	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-TSSOP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments SN74HC573ADWRG4 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments CD74HC573M96 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	125 °C	-55 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	30 ns		8:8	1
Texas Instruments SN74HC573ADW The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.	0.295 in, 7.5 mm		20-SOIC	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments SN74HC573APWR The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.	0.173 in	4.4 mm	20-TSSOP	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-TSSOP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1
Texas Instruments SN74HC573AN The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.		0.3 in	20-DIP	Through Hole	85 °C	-40 °C	D-Type Transparent Latch	20-PDIP	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1	7.62 mm
Texas Instruments CD74HC573M96G4 D-Type Transparent Latch 1 Channel 8:8 IC Tri-State 20-SOIC	0.295 in, 7.5 mm		20-SOIC	Surface Mount	125 °C	-55 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	30 ns		8:8	1
Texas Instruments SN74HC573NSR D-Type Transparent Latch 1 Channel 1:8 IC Tri-State 20-SO	0.209 in, 5.3 mm		20-SOIC	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SO	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		1:8	1
Texas Instruments SN74HC573ADWR The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up. The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.	0.295 in, 7.5 mm		20-SOIC	Surface Mount	85 °C	-40 °C	D-Type Transparent Latch	20-SOIC	2 V	6 V	7.8 mA, 7.8 mA		Tri-State	23 ns		8:8	1

Description

General part information

74HC573 Series

The SNx4HC573A devices are octal transparent D-type latches that feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q outputs respond to the data (D) inputs. When LE is low, the outputs are latched to retain the data that was set up.

Documents

Technical documentation and resources

CDx4HC573 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. C)

Data sheet

Live Insertion

Application note

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Application note

SN54/74HCT CMOS Logic Family Applications and Restrictions

Application note

CD74HC573M96

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CD74HC573M96

Deep-Dive with AI

Technical Specifications

Pricing

74HC573 Series

Description

74HC573 Series

Documents

Input and Output Characteristics of Digital Integrated Circuits

CMOS Power Consumption and CPD Calculation (Rev. B)

Power-Up Behavior of Clocked Devices (Rev. B)

Logic Guide (Rev. AB)

Signal Switch Data Book (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

LOGIC Pocket Data Book (Rev. B)

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Designing With Logic (Rev. C)

Implications of Slow or Floating CMOS Inputs (Rev. E)

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

CDx4HC573 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. C)

Live Insertion

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

SN54/74HCT CMOS Logic Family Applications and Restrictions