Technical Specifications
Parameters and characteristics for this part
| Specification | SG2525AP |
|---|---|
| Clock Sync | True |
| Control Features | Soft Start, Enable |
| Duty Cycle (Max) | 49 % |
| Frequency - Switching [Max] | 400 kHz |
| Frequency - Switching [Min] | 100 Hz |
| Function | Step-Up/Step-Down, Step-Down |
| Mounting Type | Surface Mount |
| Number of Outputs | 2 |
| Operating Temperature [Max] | 85 C |
| Operating Temperature [Min] | -25 °C |
| Output Configuration | Positive |
| Output Phases | 1 |
| Output Type | Transistor Driver |
| Package / Case | 16-SOIC |
| Package / Case [x] | 0.154 in |
| Package / Case [y] | 3.9 mm |
| Supplier Device Package | 16-SO |
| Synchronous Rectifier | True |
| Topology | Push-Pull, Buck |
| Voltage - Supply (Vcc/Vdd) [Max] | 35 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 8 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
SG2525 Series
The SG3525A series of pulse width modulator integrated circuits are designed to offer improved performance and lowered external parts count when used in designing all types of switching power supplies. The on-chip + 5.1 V reference is trimmed to ±1 % and the input common-mode range of the error amplifier includes the reference voltage eliminating external resistors. A sync input to the oscillator allows multiple units to be slaved or a single unit to be synchronized to an external system clock. A single resistor between the CTand the discharge terminals provide a wide range of dead time ad- justment.These devices also feature built-in soft-start circuitry with only an external timing capacitor required. A shutdown terminal controls both the soft-start circuity and the output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown,as well as soft-start recycle with longer shutdown commands. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for sub-normal input voltages. This lockout circuitry includes approximately 500 mV of hysteresis for jitter-free operation. Another feature of these PWM circuits is a latch following the comparator. Once a PWM pulses has been terminated for any reason,the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200 mA. The SG3525A output stage features NOR logic, giving a LOW output for an OFF state.
Documents
Technical documentation and resources
