
TPS53689RSBT
ActiveDUAL-CHANNEL, 8 PHASE STEP-DOWN, DIGITAL MULTIPHASE D-CAP+™ CONTROLLER WITH VR14 SVID AND PMBUS
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TPS53689RSBT
ActiveDUAL-CHANNEL, 8 PHASE STEP-DOWN, DIGITAL MULTIPHASE D-CAP+™ CONTROLLER WITH VR14 SVID AND PMBUS
Technical Specifications
Parameters and characteristics commom to parts in this series
Specification | TPS53689RSBT | TPS53689 Series |
---|---|---|
Applications | Intel VR14, Controller | Intel VR14, Controller |
Mounting Type | Surface Mount | Surface Mount |
Number of Outputs [custom] | 2 | 2 |
Operating Temperature [Max] | 125 °C | 125 °C |
Operating Temperature [Min] | -40 °C | -40 °C |
Package / Case | 40-WFQFN Exposed Pad | 40-WFQFN Exposed Pad |
Supplier Device Package | 40-WQFN (5x5) | 40-WQFN (5x5) |
Voltage - Input [Max] | 17 V | 17 V |
Voltage - Input [Min] | 4.5 V | 4.5 V |
Voltage - Output [Max] | 5.5 V | 5.5 V |
Voltage - Output [Min] | 0.25 V | 0.25 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
TPS53689 Series
Dual-channel, 8 phase step-down, digital multiphase D-CAP+™ controller with VR14 SVID and PMBus
Part | Mounting Type | Number of Outputs [custom] | Supplier Device Package | Package / Case | Applications | Voltage - Output [Max] | Voltage - Output [Min] | Voltage - Input [Min] | Voltage - Input [Max] | Operating Temperature [Max] | Operating Temperature [Min] |
---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments TPS53689RSBRThe TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C. | Surface Mount | 2 | 40-WQFN (5x5) | 40-WFQFN Exposed Pad | Controller, Intel VR14 | 5.5 V | 0.25 V | 4.5 V | 17 V | 125 °C | -40 °C |
Texas Instruments TPS53689RSBTThe TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C. | Surface Mount | 2 | 40-WQFN (5x5) | 40-WFQFN Exposed Pad | Controller, Intel VR14 | 5.5 V | 0.25 V | 4.5 V | 17 V | 125 °C | -40 °C |
Description
General part information
TPS53689 Series
The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
The TPS53689 device is offered in a thermally enhanced 40-pin QFN packaged and is rated to operate from –40°C to 125°C.
The TPS53689 is a VR14 SVID compliant step down controller with two channels, built-in non-volatile memory (NVM), and PMBus™ interface, and is fully compatible with TI NexFET™ power stages. Advanced control features such as the D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, low output capacitance, and good dynamic current sharing. The device also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at different loads. Adjustable control of output voltage slew rate and adaptive voltage positioning are natively supported. In addition, the device supports the PMBus communication interface for reporting the telemetry of voltage, current, power, temperature, and fault conditions to the host system. All programmable parameters can be configured through the PMBus interface and can be stored in NVM as the new default values, to minimize the external component count.
Documents
Technical documentation and resources