The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations such as: 2-level priority data buffering, Bidirectional operation, Width expansion and Depth expansion.