Technical Specifications
Parameters and characteristics for this part
| Specification | STM32L476VGT3 | 
|---|---|
| Connectivity | SAI, EBI/EMI, QSPI, CANbus, I2C, SWPMI, LINbus, SPI, MMC/SD, UART/USART, IrDA, USB OTG | 
| Core Processor | ARM® Cortex®-M4 | 
| Core Size | 32-Bit Single-Core | 
| Data Converters | |
| Data Converters [custom] | 12 b | 
| Data Converters [custom] | 16 | 
| Mounting Type | Surface Mount | 
| Number of I/O | 82 | 
| Operating Temperature [Max] | 125 °C | 
| Operating Temperature [Min] | -40 °C | 
| Oscillator Type | Internal | 
| Package / Case | 100-LQFP | 
| Peripherals | LCD, DMA, Brown-out Detect/Reset, WDT, PWM | 
| Program Memory Size | 1 MB | 
| Program Memory Type | FLASH | 
| RAM Size | 128 K | 
| Speed | 80 MHz | 
| Supplier Device Package | 100-LQFP (14x14) | 
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V | 
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V | 
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
P-NUCLEO-AZURE1 Series
The STM32L476xx devices are ultra-low-power microcontrollers based on the high-performance Arm®Cortex®-M4 32-bit RISC core operating at a frequency of up to 80 MHz. The Cortex-M4 core features a Floating point unit (FPU) single precision that supports all Arm®single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) which enhances application security.
The STM32L476xx devices embed high-speed memories (flash memory up to 1 Mbyte, up to 128 Kbyte of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad SPI flash memories interface (available on all packages) and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
The STM32L476xx devices embed several protection mechanisms for embedded flash memory and SRAM: readout protection, write protection, proprietary code readout protection and Firewall.
Documents
Technical documentation and resources
