
74LVC2G00HK3-7
ActiveNAND GATE, LVC/LCX/Z SERIES, 2-FUNC, 2-INPUT, CMOS, PDSO8, X2-DFN1410-8
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74LVC2G00HK3-7
ActiveNAND GATE, LVC/LCX/Z SERIES, 2-FUNC, 2-INPUT, CMOS, PDSO8, X2-DFN1410-8
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Technical Specifications
Parameters and characteristics for this part
| Specification | 74LVC2G00HK3-7 |
|---|---|
| Current - Output High, Low [x] | 32 mA |
| Current - Output High, Low [y] | 32 mA |
| Current - Quiescent (Max) [Max] | 40 µA |
| Input Logic Level - High [Max] | 3.85 V |
| Input Logic Level - High [Min] | 1.07 V |
| Input Logic Level - Low [Max] | 1.65 V |
| Input Logic Level - Low [Min] | 0.58 V |
| Logic Type | NAND Gate |
| Max Propagation Delay @ V, Max CL | 4.2 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 2 |
| Number of Inputs | 2 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 8-XFDFN |
| Supplier Device Package | X2-DFN1410-8 |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 1.65 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Arrow | N/A | 5000 | $ 0.04 | |
| Digikey | Cut Tape (CT) | 1 | $ 0.43 | |
| 10 | $ 0.32 | |||
| 25 | $ 0.28 | |||
| 100 | $ 0.18 | |||
| 250 | $ 0.15 | |||
| 500 | $ 0.12 | |||
| 1000 | $ 0.09 | |||
| 2500 | $ 0.08 | |||
| Digi-Reel® | 1 | $ 0.43 | ||
| 10 | $ 0.32 | |||
| 25 | $ 0.28 | |||
| 100 | $ 0.18 | |||
| 250 | $ 0.15 | |||
| 500 | $ 0.12 | |||
| 1000 | $ 0.09 | |||
| 2500 | $ 0.08 | |||
| Tape & Reel (TR) | 5000 | $ 0.07 | ||
| 10000 | $ 0.06 | |||
| 25000 | $ 0.06 | |||
| 50000 | $ 0.05 | |||
| 125000 | $ 0.05 | |||
Description
General part information
74LVC2G00 Series
The 74LVC2G00 is a dual two input NAND gate. Both gates have push-pull outputs designed for operation over a power supply range of 1.65V to 5.5V. The device is fully specified for partial power down applications using IOFF. The IOFFcircuitry disables the output preventing damaging current backflow when the device is powered down.
Documents
Technical documentation and resources