SN74AHC04DBR
ActiveTexas Instruments
6-CH, 2-V TO 5.5-V INVERTERS
SN74AHC04DBR
ActiveTexas Instruments
6-CH, 2-V TO 5.5-V INVERTERS
Description
General part information
74AHC04 Series
The ’AHC04 devices contain six independent inverters. These devices perform the Boolean function Y = A.
The ’AHC04 devices contain six independent inverters. These devices perform the Boolean function Y = A.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHC04DBR |
|---|---|
| Current - Output High | 8 mA |
| Current - Output Low | 8 mA |
| Current - Quiescent (Max) | 2 µA |
| Input Logic Level - High (Max) | 3.85 V |
| Input Logic Level - High (Min) | 1.5 V |
| Input Logic Level - Low (Max) | 1.65 V |
| Input Logic Level - Low (Min) | 0.5 V |
| Logic Type | Inverter |
| Max CL | 50 pF |
| Max Propagation Delay | 7.5 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 6 |
| Number of Inputs | 1 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -40 °C |
| Package Length | 0.209 in |
| Package Name | 14-SSOP |
| Package Width | 5.3 mm |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 2 V |
Pricing
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CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
Texas Instruments Little Logic Application Report
LOGIC Pocket Data Book (Rev. B)
SNx4AHC04 HEX INVERTERS datasheet (Rev. P)
Live Insertion
Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)
Selecting the Right Level Translation Solution (Rev. A)
Logic Guide (Rev. AB)
How to Select Little Logic (Rev. A)
AHC/AHCT Designer's Guide February 2000 (Rev. D)
CMOS Power Consumption and CPD Calculation (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Implications of Slow or Floating CMOS Inputs (Rev. E)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Design Summary for WCSP Little Logic (Rev. B)
Little Logic Guide 2018 (Rev. G)