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2ED21064S06JXUMA1 - PG-DSO-14

2ED21064S06JXUMA1

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Infineon Technologies

THE 2ED21064S06J IS A 650 V, 0.7 A HIGH-SIDE AND LOW-SIDE GATE DRIVER WITH INTEGRATED BOOTSTRAP DIODE (DSO-14 PACKAGE)

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2ED21064S06JXUMA1 - PG-DSO-14

2ED21064S06JXUMA1

Active
Infineon Technologies

THE 2ED21064S06J IS A 650 V, 0.7 A HIGH-SIDE AND LOW-SIDE GATE DRIVER WITH INTEGRATED BOOTSTRAP DIODE (DSO-14 PACKAGE)

Deep-Dive with AI

DocumentsDatasheet

Technical Specifications

Parameters and characteristics for this part

Specification2ED21064S06JXUMA1
Channel TypeIndependent
Current - Peak Output (Source, Sink) [custom]700 mA
Current - Peak Output (Source, Sink) [custom]290 mA
Driven ConfigurationHigh-Side and Low-Side
Gate TypeN-Channel MOSFET, IGBT
High Side Voltage - Max (Bootstrap) [Max]20 V
Logic Voltage - VIL, VIH [custom]1.1 V
Logic Voltage - VIL, VIH [custom]1.7 V
Mounting TypeSurface Mount
Number of Drivers2
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Package / Case14-SOIC
Package / Case [x]0.154 in
Package / Case [y]3.9 mm
Rise / Fall Time (Typ) [custom]35 ns
Rise / Fall Time (Typ) [custom]100 ns
Supplier Device PackagePG-DSO-14
Voltage - Supply [Max]20 V
Voltage - Supply [Min]10 VDC

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
DigikeyCut Tape (CT) 1$ 1.72
10$ 1.55
25$ 1.46
100$ 1.25
250$ 1.17
500$ 1.02
1000$ 0.85
Digi-Reel® 1$ 1.72
10$ 1.55
25$ 1.46
100$ 1.25
250$ 1.17
500$ 1.02
1000$ 0.85
Tape & Reel (TR) 2500$ 0.79
5000$ 0.76
12500$ 0.73
NewarkEach (Supplied on Cut Tape) 1$ 1.09
10$ 0.99
25$ 0.93
50$ 0.87
100$ 0.81

Description

General part information

2ED21064 Series

650 Vhigh and low sidehigh speed powerMOSFETandIGBTgate driver with typical 0.29 source current, and 0.7 sink current in DSO-14 package. The smaller DSO-8 package version is also available:2ED2106S06F. Based onInfineon’s SOI-technology, having excellent ruggedness and noise immunity against negative transient voltages on VS pin. No parasitic thyristor structures present in the device, hence no parasitic latch up at all temperature and voltage conditions.

Documents

Technical documentation and resources