CY7C1020DV33-10ZSXI

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Infineon Technologies

SRAM, ASYNCHRONOUS SRAM, 512 KBIT, 32K X 16BIT, TSOP, 44 PINS, 3 V

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CY7C1020DV33-10ZSXI

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Infineon Technologies

SRAM, ASYNCHRONOUS SRAM, 512 KBIT, 32K X 16BIT, TSOP, 44 PINS, 3 V

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Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics for this part

Specification	CY7C1020DV33-10ZSXI

Access Time	10 ns
Memory Format	SRAM
Memory Interface	Parallel
Memory Size	64 kb
Memory Type	Volatile
Mounting Type	Surface Mount
Operating Temperature [Max]	85 °C
Operating Temperature [Min]	-40 °C
Package / Case	10.16 mm
Package / Case	10.16 mm
Package / Case	44-TSOP
Supplier Device Package	44-TSOP II
Technology	SRAM - Asynchronous
Voltage - Supply [Max]	3.6 V
Voltage - Supply [Min]	3 V
Write Cycle Time - Word, Page	10 ns

CY7C1020 Series

Part	Access Time	Memory Type	Mounting Type	Operating Temperature [Max]	Operating Temperature [Min]	Memory Format	Package / Case	Package / Case	Package / Case	Memory Size	Technology	Write Cycle Time - Word, Page	Voltage - Supply [Min]	Voltage - Supply [Max]	Supplier Device Package	Memory Interface	Package / Case
Infineon Technologies CY7C1020D-10ZSXI	10 ns	Volatile	Surface Mount	85 °C	-40 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	10 ns	4.5 V	5.5 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020D-10ZSXIT	10 ns	Volatile	Surface Mount	85 °C	-40 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	10 ns	4.5 V	5.5 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020CV26-15ZSXEKJ	15 ns	Volatile	Surface Mount	125 °C	-40 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	15 ns	2.5 V	2.7 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020D-10ZSXI	10 ns	Volatile	Surface Mount	85 °C	-40 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	10 ns	4.5 V	5.5 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020B-12VC	12 ns	Volatile	Surface Mount	70 °C	0 °C	SRAM	10.16 mm		44-BSOJ	64 kb	SRAM - Asynchronous	12 ns	4.5 V	5.5 V		Parallel	10.16 mm
Infineon Technologies CY7C1020BN-12ZXCT	12 ns	Volatile	Surface Mount	70 °C	0 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	12 ns	4.5 V	5.5 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020B-15VC	15 ns	Volatile	Surface Mount	70 °C	0 °C	SRAM	10.16 mm		44-BSOJ	64 kb	SRAM - Asynchronous	15 ns	4.5 V	5.5 V		Parallel	10.16 mm
Infineon Technologies CY7C1020BN-12ZXC	12 ns	Volatile	Surface Mount	70 °C	0 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	12 ns	4.5 V	5.5 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020DV33-10ZSXI	10 ns	Volatile	Surface Mount	85 °C	-40 °C	SRAM	10.16 mm	10.16 mm	44-TSOP	64 kb	SRAM - Asynchronous	10 ns	3 V	3.6 V	44-TSOP II	Parallel
Infineon Technologies CY7C1020-15VC	15 ns	Volatile	Surface Mount	70 °C	0 °C	SRAM	10.16 mm		44-BSOJ	64 kb	SRAM - Asynchronous	15 ns	4.5 V	5.5 V		Parallel	10.16 mm

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Bulk	150	$ 3.91
		150	$ 3.91
	Tray	1	$ 6.36
		1	$ 6.36
		10	$ 5.81
		10	$ 5.81
		25	$ 5.70
		25	$ 5.70
		40	$ 5.65
		40	$ 5.65
		135	$ 5.07
		135	$ 5.07
		270	$ 5.05
		270	$ 5.05
		540	$ 4.74
		540	$ 4.74
		945	$ 4.54
		945	$ 4.54
Newark	Each	1	$ 5.53
		10	$ 4.97
		25	$ 4.80
		50	$ 4.80
		100	$ 4.79
		250	$ 4.79
		540	$ 4.79

Description

General part information

CY7C1020 Series

CY7C1020DV33-10ZSXI is a CY7C1020DV33 high-performance CMOS static RAM organized as 32,768 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking chip enable (CE) and write enable (WE) inputs low. If byte low enable (BLE) is low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A14). If byte high enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A14). Reading from the device is accomplished by taking chip enable active-low (CE) and output enable (OE) low while forcing the write enable (WE) high. If byte low enable (BLE) is low, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If byte high enable (BHE) is low, then data from memory will appear on I/O8 to I/O15.

Documents

Technical documentation and resources