CD54HC193F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BINARY UP/DOWN COUNTERS
Deep-Dive with AI
Search across all available documentation for this part.
CD54HC193F3A
ActiveHIGH SPEED CMOS LOGIC PRESETTABLE SYNCHRONOUS 4-BIT BINARY UP/DOWN COUNTERS
Deep-Dive with AI
Technical Specifications
Parameters and characteristics for this part
| Specification | CD54HC193F3A |
|---|---|
| Count Rate | 29 MHz |
| Direction | Down, Up |
| Logic Type | Binary Counter |
| Mounting Type | Through Hole |
| Number of Bits per Element | 4 |
| Number of Elements [custom] | 1 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -55 C |
| Package / Case | 16-CDIP (0.300", 7.62mm) |
| Reset | Asynchronous |
| Supplier Device Package | 16-CDIP |
| Timing | Synchronous |
| Trigger Type | Positive Edge |
| Voltage - Supply [Max] | 6 V |
| Voltage - Supply [Min] | 2 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
54HC193 Series
High Speed CMOS Logic Presettable Synchronous 4-Bit Binary Up/Down Counters
| Part | Trigger Type | Mounting Type | Direction | Number of Elements [custom] | Reset | Voltage - Supply [Max] | Voltage - Supply [Min] | Count Rate | Operating Temperature [Min] | Operating Temperature [Max] | Logic Type | Timing | Supplier Device Package | Package / Case | Number of Bits per Element |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD54HC193F3AThe ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram. | Positive Edge | Through Hole | Down, Up | 1 | Asynchronous | 6 V | 2 V | 29 MHz | -55 C | 125 °C | Binary Counter | Synchronous | 16-CDIP | 16-CDIP (0.300", 7.62mm) | 4 |
Description
General part information
54HC193 Series
The ’HC192, ’HC193 and ’HCT193 are asynchronously presettable BCD Decade and Binary Up/Down synchronous counters, respectively.
Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL)\. The counter is incremented on the low-to-high transition of the Clock-Up input (and a high level on the Clock-Down input) and decremented on the low to high transition of the Clock-Down input (and a high level on the Clock-up input). A high level on the MR input overrides any other input to clear the counter to its zero state. The Terminal Count up (carry) goes low half a clock period before the zero count is reached and returns to a high level at the zero count. The Terminal Count Down (borrow) in the count down mode likewise goes low half a clock period before the maximum count (9 in the 192 and 15 in the 193) and returns to high at the maximum count. Cascading is effected by connecting the carry and borrow outputs of a less significant counter to the Clock-Up and CLock-Down inputs, respectively, of the next most significant counter.
If a decade counter is present to an illegal state or assumes an illegal state when power is applied, it will return to the normal sequence in one count as shown in state diagram.
Documents
Technical documentation and resources