CD74HC597M

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Texas Instruments

HIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE

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Search across all available documentation for this part.

DocumentsDesigning With Logic (Rev. C)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+13

CD74HC597M

Active

Texas Instruments

HIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE

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DocumentsDesigning With Logic (Rev. C)Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)+13

Specifications Pricing Series Description Documents

Technical Specifications

Parameters and characteristics commom to parts in this series

Specification	CD74HC597M	74HC597 Series

Function	Parallel or Serial to Serial	Parallel or Serial to Serial
Logic Type	Shift Register	Shift Register
Mounting Type	Surface Mount	Surface Mount, Through Hole
Number of Bits per Element	8	8
Number of Elements [custom]	1	1
Operating Temperature [Max]	125 °C	125 °C
Operating Temperature [Min]	-55 °C	-55 °C
Output Type	Push-Pull	Push-Pull
Package / Case	16-SOIC	16-SOIC, 16-DIP
Package / Case	3.9 mm Width, 0.154 in	0.154 - 7.62 mm Width
Supplier Device Package	16-SOIC	16-SOIC, 16-PDIP
Voltage - Supply [Max]	6 V	6 V
Voltage - Supply [Min]	2 V	2 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

Distributor	Package	Quantity	$

Digikey	Tube	1	$ 1.96
		10	$ 1.25
		25	$ 1.06
		100	$ 0.85
		250	$ 0.75
		536	$ 0.56
Texas Instruments	TUBE	1	$ 0.96
		100	$ 0.74
		250	$ 0.54
		1000	$ 0.39

74HC597 Series

HIGH SPEED CMOS LOGIC 8-BIT SHIFT REGISTER WITH INPUT STORAGE

Part	Operating Temperature [Min]	Operating Temperature [Max]	Function	Number of Elements [custom]	Output Type	Supplier Device Package	Mounting Type	Logic Type	Number of Bits per Element	Package / Case	Package / Case	Voltage - Supply [Min]	Voltage - Supply [Max]
Texas Instruments CD74HC597M The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597MT The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597M96E4 Shift Shift Register 1 Element 8 Bit 16-SOIC	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597EG4 Shift Shift Register 1 Element 8 Bit 16-PDIP	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-PDIP	Through Hole	Shift Register	8	16-DIP	0.3 in, 7.62 mm	2 V	6 V
Texas Instruments CD74HC597M96G4 Shift Shift Register 1 Element 8 Bit 16-SOIC	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597M96 The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597MG4 Shift Shift Register 1 Element 8 Bit 16-SOIC	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-SOIC	Surface Mount	Shift Register	8	16-SOIC	0.154 in, 3.9 mm Width	2 V	6 V
Texas Instruments CD74HC597E The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high. The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.	-55 °C	125 °C	Parallel or Serial to Serial	1	Push-Pull	16-PDIP	Through Hole	Shift Register	8	16-DIP	0.3 in, 7.62 mm	2 V	6 V

Description

General part information

74HC597 Series

The ’HC597 and CD74HCT597 are high-speed silicon gate CMOS devices that are pin compatible with the LSTTL 597 devices. Each device consists of an 8-flip-flop input register and an 8-bit parallel-in/serial-in, serial-out shift register. Each register is controlled by its own clock. A "low" on the parallel load input (PL\) shifts parallel stored data asynchronously into the shift register. A "low" master input (MR\) clears the shift register. Serial input data can also be synchronously shifted through the shift register when PL\ is high.

Documents

Technical documentation and resources

CD74HC597M

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CD74HC597M

Deep-Dive with AI

Technical Specifications

Pricing

74HC597 Series

Description

74HC597 Series

Documents

Designing With Logic (Rev. C)

Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)

Power-Up Behavior of Clocked Devices (Rev. B)

CD54HC597, CD74HC597, CD74HCT597 datasheet (Rev. C)

Live Insertion

Signal Switch Data Book (Rev. A)

TI IBIS File Creation, Validation, and Distribution Processes

Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc

Semiconductor Packing Material Electrostatic Discharge (ESD) Protection

LOGIC Pocket Data Book (Rev. B)

CMOS Power Consumption and CPD Calculation (Rev. B)

Logic Guide (Rev. AB)

Input and Output Characteristics of Digital Integrated Circuits

Implications of Slow or Floating CMOS Inputs (Rev. E)

SN54/74HCT CMOS Logic Family Applications and Restrictions