Technical Specifications
Parameters and characteristics for this part
| Specification | SPC564A80L7CFBR |
|---|---|
| Connectivity | SPI, SCI, CANbus, LINbus, EBI/EMI |
| Core Processor | e200z4 |
| Core Size | 32-Bit Single-Core |
| Data Converters [custom] | 34 |
| Data Converters [custom] | 12 b |
| Grade | Automotive |
| Mounting Type | Surface Mount |
| Number of I/O | 118 |
| Operating Temperature [Max] | 125 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 176-LQFP |
| Peripherals | WDT, DMA, PWM, POR |
| Program Memory Size | 4 MB |
| Program Memory Type | FLASH |
| Qualification | AEC-Q100 |
| RAM Size | 192 K |
| Speed | 120 MHz |
| Supplier Device Package | 176-LQFP (24x24) |
| Voltage - Supply (Vcc/Vdd) [Max] | 1.32 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.14 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tape & Reel (TR) | 500 | $ 20.26 | |
Description
General part information
SPC564A70L7 Series
The Leopard series microcontrollers are system-on-chip devices that are built on Power Architecture technology and contain enhancements that improve the architecture’s fit in embedded applications, include additional instruction support for digital signal processing (DSP) and integrate technologies such as an enhanced time processor unit, enhanced queued analog-to-digital converter, Controller Area Network, and an enhanced modular input-output system.
The SPC56XL60/54 family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers. It belongs to an expanding range of automotive-focused products designed to address electrical hydraulic power steering (EHPS), electric power steering (EPS) and airbag applications. The advanced and cost-efficient host processor core of the SPC56XL60/54 automotive controller family complies with the Power Architecture embedded category. It operates at speeds as high as 120 MHz and offers high-performance processing optimized for low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and is supported with software drivers, operating systems and configuration code to assist with users’ implementations.
Documents
Technical documentation and resources