CD74HCT7046AM96
ActiveHIGH SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
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CD74HCT7046AM96
ActiveHIGH SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO AND LOCK DETECTOR
Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | CD74HCT7046AM96 | 74HCT7046 Series |
|---|---|---|
| - | - | |
| Differential - Input:Output [custom] | False | False |
| Differential - Input:Output [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Divider/Multiplier [custom] | False | False |
| Frequency - Max [Max] | 38 MHz | 38 MHz |
| Input | CMOS | CMOS |
| Mounting Type | Surface Mount | Through Hole, Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 125 °C | 125 °C |
| Operating Temperature [Min] | -55 °C | -55 °C |
| Output | CMOS | CMOS |
| Package / Case | 16-SOIC | 16-DIP, 16-SOIC |
| Package / Case | 3.9 mm Width, 0.154 in | 0.154 - 7.62 in |
| PLL | True | True |
| Ratio - Input:Output [custom] | 1 | 1 |
| Ratio - Input:Output [custom] | 2 | 2 |
| Supplier Device Package | 16-SOIC | 16-PDIP, 16-SOIC |
| Type | Phase Lock Loop (PLL) | Phase Lock Loop (PLL) |
| Voltage - Supply [Max] | 5.5 V | 5.5 V |
| Voltage - Supply [Min] | 4.5 V | 4.5 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 2.74 | |
| 10 | $ 2.46 | |||
| 25 | $ 2.33 | |||
| 100 | $ 2.02 | |||
| 250 | $ 1.92 | |||
| 500 | $ 1.72 | |||
| 1000 | $ 1.45 | |||
| Digi-Reel® | 1 | $ 2.74 | ||
| 10 | $ 2.46 | |||
| 25 | $ 2.33 | |||
| 100 | $ 2.02 | |||
| 250 | $ 1.92 | |||
| 500 | $ 1.72 | |||
| 1000 | $ 1.45 | |||
| Tape & Reel (TR) | 2500 | $ 1.37 | ||
| 5000 | $ 1.30 | |||
| 7500 | $ 1.28 | |||
| Texas Instruments | LARGE T&R | 1 | $ 2.38 | |
| 100 | $ 2.09 | |||
| 250 | $ 1.46 | |||
| 1000 | $ 1.18 | |||
74HCT7046 Series
High Speed CMOS Logic Phase-Locked Loop with VCO and Lock Detector
| Part | Operating Temperature [Min] | Operating Temperature [Max] | PLL | Differential - Input:Output [custom] | Differential - Input:Output [custom] | Divider/Multiplier [custom] | Divider/Multiplier [custom] | Voltage - Supply [Max] | Voltage - Supply [Min] | Package / Case | Package / Case | Output | Frequency - Max [Max] | Ratio - Input:Output [custom] | Ratio - Input:Output [custom] | Supplier Device Package | Mounting Type | Input | Type | Number of Circuits |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Texas Instruments CD74HCT7046AE | -55 °C | 125 °C | 5.5 V | 4.5 V | 0.3 in, 7.62 mm | 16-DIP | CMOS | 38 MHz | 1 | 2 | 16-PDIP | Through Hole | CMOS | Phase Lock Loop (PLL) | 1 | |||||
Texas Instruments CD74HCT7046AM96 | -55 °C | 125 °C | 5.5 V | 4.5 V | 0.154 in, 3.9 mm Width | 16-SOIC | CMOS | 38 MHz | 1 | 2 | 16-SOIC | Surface Mount | CMOS | Phase Lock Loop (PLL) | 1 | |||||
Texas Instruments CD74HCT7046AEG4 | -55 °C | 125 °C | 5.5 V | 4.5 V | 0.3 in, 7.62 mm | 16-DIP | CMOS | 38 MHz | 1 | 2 | 16-PDIP | Through Hole | CMOS | Phase Lock Loop (PLL) | 1 | |||||
Texas Instruments 74HCT7046AM96 |
Description
General part information
74HCT7046 Series
The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input amplifiers. With a passive low-pass filter, the 7046A forms a second-order loop PLL. The excellent VCO linearity is achieved by the use of linear op-amp techniques.
The CD74HC7046A and CD74HCT7046A high-speed silicon-gate CMOS devices, specified in compliance with JEDEC Standard No. 7A, are phase-locked-loop (PLL) circuits that contain a linear voltage-controlled oscillator (VCO), two-phase comparators (PC1, PC2), and a lock detector. A signal input and a comparator input are common to each comparator. The lock detector gives a HIGH level at pin 1 (LD) when the PLL is locked. The lock detector capacitor must be connected between pin 15 (CLD) and pin 8 (Gnd). For a frequency range of 100kHz to 10MHz, the lock detector capacitor should be 1000pF to 10pF, respectively.
Documents
Technical documentation and resources