Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | MC100EPT25MNR4G | MC100EPT25 Series |
|---|---|---|
| Channel Type | Unidirectional | Unidirectional |
| Channels per Circuit | 1 | 1 |
| Input Signal | ECL | ECL |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 °C |
| Output Signal | LVTTL | LVTTL |
| Output Type | Non-Inverted | Non-Inverted |
| Package / Case | 8-VFDFN Exposed Pad | 8-MSOP, 8-TSSOP, 8-VFDFN Exposed Pad |
| Package / Case | - | 0.118 in |
| Package / Case | - | 3 mm |
| Supplier Device Package | 8-DFN (2x2) | 8-TSSOP, 8-DFN (2x2) |
| Translator Type | Mixed Signal | Mixed Signal |
MC100EPT25 Series
Translator, Differential LVECL / ECL to LVTTL
| Part | Channel Type | Channels per Circuit | Supplier Device Package | Package / Case | Package / Case [custom] | Package / Case | Translator Type | Mounting Type | Input Signal | Output Type | Operating Temperature [Max] | Operating Temperature [Min] | Output Signal | Number of Circuits |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ON Semiconductor MC100EPT25DTR2G | Unidirectional | 1 | 8-TSSOP | 8-MSOP, 8-TSSOP | 0.118 in | 3 mm | Mixed Signal | Surface Mount | ECL | Non-Inverted | 85 °C | -40 °C | LVTTL | 1 |
ON Semiconductor MC100EPT25MNR4G | Unidirectional | 1 | 8-DFN (2x2) | 8-VFDFN Exposed Pad | Mixed Signal | Surface Mount | ECL | Non-Inverted | 85 °C | -40 °C | LVTTL | 1 |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
Description
General part information
MC100EPT25 Series
The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.The VBBoutput allows the EPT25 to also be used in a single-ended input mode. In this mode the VBBoutput is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the VBBpin should be bypassed to ground with at least a 0.01 µF capacitor.
Documents
Technical documentation and resources