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STPIC6C595TTR - NXP MC68HC908QY1VDTE

STPIC6C595TTR

Active
STMicroelectronics

SHIFT REGISTER, STPIC6C595, SERIAL TO PARALLEL, 1 ELEMENT, 8 -BIT, 16 PINS, TSSOP

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STPIC6C595TTR - NXP MC68HC908QY1VDTE

STPIC6C595TTR

Active
STMicroelectronics

SHIFT REGISTER, STPIC6C595, SERIAL TO PARALLEL, 1 ELEMENT, 8 -BIT, 16 PINS, TSSOP

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Technical Specifications

Parameters and characteristics for this part

SpecificationSTPIC6C595TTR
FunctionSerial to Parallel, Serial
Logic TypeShift Register
Mounting TypeSurface Mount
Number of Bits per Element8
Number of Elements1
Operating Temperature [Max]125 °C
Operating Temperature [Min]-40 °C
Output TypeOpen Drain
Package / Case16-TSSOP
Package / Case [x]0.173 in
Package / Case [y]4.4 mm
Supplier Device Package16-TSSOP
Voltage - Supply [Max]5.5 V
Voltage - Supply [Min]4.5 V

Pricing

Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly

DistributorPackageQuantity$
ArrowN/A 2500$ 0.39
5000$ 0.32
DigikeyCut Tape (CT) 1$ 1.13
10$ 1.01
25$ 0.96
100$ 0.79
250$ 0.74
500$ 0.65
1000$ 0.52
Digi-Reel® 1$ 1.13
10$ 1.01
25$ 0.96
100$ 0.79
250$ 0.74
500$ 0.65
1000$ 0.52
Tape & Reel (TR) 2500$ 0.48
5000$ 0.46
12500$ 0.44

Description

General part information

STPIC6C595 Series

This STPIC6C595 is a monolithic, medium-voltage, low current power 8-bit shift register designed for use in systems that require relatively moderate load power such as LEDs. The device contains a built-in voltage clamp on the outputs for inductive transient protection. Power driver applications include relays, solenoids, and other low-current or medium-voltage loads.

The device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage register. Data transfers through both the shift and storage register clock (SRCK) and the register clock (RCK), respectively. The device transfers data out the serial output (SER OUT) port on the rising edge of SRCK. The storage register transfers data to the output buffer when shift register clear (CLR) is high. WhenCLRis low, the input shift register is cleared. When output enable (G) is held high, all data in the output buffer is held low and all drain output are off. When G is held low, data from the storage register is transparent to the output buffer.

When data in the output buffers is low, the DMOS transistor outputs are off. When data is high, the DMOS transistor outputs have sink-current capability. The SER OUT allows for cascading of the data from the shift register to additional devices.