SN74AHCT1G00DCKT
ObsoleteTexas Instruments
SINGLE 2-INPUT, 4.5-V TO 5.5-V NAND GATE WITH TTL-COMPATIBLE CMOS INPUTS
SN74AHCT1G00DCKT
ObsoleteTexas Instruments
SINGLE 2-INPUT, 4.5-V TO 5.5-V NAND GATE WITH TTL-COMPATIBLE CMOS INPUTS
Description
General part information
SN74AHCT1G00 Series
The SN74AHCT1G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.
The SN74AHCT1G00 device performs the Boolean function Y = A × B or Y = A + B in positive logic.
Technical Specifications
Parameters and characteristics for this part
| Specification | SN74AHCT1G00DCKT |
|---|---|
| Current - Output High | 8 mA |
| Current - Output Low | 8 mA |
| Current - Quiescent (Max) | 1 µA |
| Input Logic Level - High | 2 V |
| Input Logic Level - Low (Voltage) | 0.8 V |
| Logic Type | NAND Gate |
| Max CL | 15 pF |
| Max Propagation Delay | 7.9 ns |
| Mounting Type | Surface Mount |
| Number of Circuits | 1 |
| Number of Inputs | 2 |
| Operating Temperature (Max) | 125 °C |
| Operating Temperature (Min) | -40 °C |
| Package / Case | SOT-353, SC-70-5, 5-TSSOP |
| Package Name | SC-70-5 |
| Voltage - Supply (Maximum) | 5.5 V |
| Voltage - Supply (Minimum) | 4.5 V |
Pricing
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CAD
3D models and CAD resources for this part
Documents
Technical documentation and resources
How to Select Little Logic (Rev. A)
LOGIC Pocket Data Book (Rev. B)
Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
Live Insertion
Implications of Slow or Floating CMOS Inputs (Rev. E)
SN74AHCT1G00 Single 2-Input Positive-NAND Gate datasheet (Rev. P)
Advanced High-Speed CMOS (AHC) Logic Family (Rev. C)
Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
AHC/AHCT Designer's Guide February 2000 (Rev. D)
Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)
Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices
Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C)
Little Logic Guide 2018 (Rev. G)
Texas Instruments Little Logic Application Report
Logic Guide (Rev. AB)
CMOS Power Consumption and CPD Calculation (Rev. B)
Design Summary for WCSP Little Logic (Rev. B)
TI IBIS File Creation, Validation, and Distribution Processes
Selecting the Right Level Translation Solution (Rev. A)
