Technical Specifications
Parameters and characteristics for this part
| Specification | STM32G474VBT6 |
|---|---|
| Connectivity | I2C, IrDA, QSPI, CANbus, UART/USART, LINbus, SPI |
| Core Processor | ARM® Cortex®-M4F |
| Core Size | 32-Bit Single-Core |
| Data Converters | D/A 7x12b, A/D 42x12b |
| Mounting Type | Surface Mount |
| Number of I/O | 86 |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Oscillator Type | Internal |
| Package / Case | 100-LQFP |
| Peripherals | Brown-out Detect/Reset, DMA, POR, WDT, PWM, I2S |
| Program Memory Size | 128 KB |
| Program Memory Type | FLASH |
| RAM Size | 128 K |
| Supplier Device Package | 100-LQFP (14x14) |
| Voltage - Supply (Vcc/Vdd) [Max] | 3.6 V |
| Voltage - Supply (Vcc/Vdd) [Min] | 1.71 V |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tray | 1 | $ 7.97 | |
| 10 | $ 7.20 | |||
| 25 | $ 6.86 | |||
| 80 | $ 5.96 | |||
| 100 | $ 4.81 | |||
| 230 | $ 5.69 | |||
| 250 | $ 4.59 | |||
| 540 | $ 5.19 | |||
| 1080 | $ 4.52 | |||
Description
General part information
NUCLEO-G474RE Series
The STM32G474xB/xC/xE devices are based on the high-performance Arm®Cortex®-M4 32-bit RISC core. They operate at a frequency of up to 170 MHz.
The Cortex-M4 core features a single-precision floating-point unit (FPU), which supports all the Arm single-precision data-processing instructions and all the data types. It also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) which enhances the application’s security.
These devices embed high-speed memories (up to 512 Kbytes of Flash memory, and 128 Kbytes of SRAM), a flexible external memory controller (FSMC) for static memories (for devices with packages of 100 pins and more), a Quad-SPI Flash memory interface, and an extensive range of enhanced I/Os and peripherals connected to two APB buses, two AHB buses and a 32-bit multi-AHB bus matrix.
Documents
Technical documentation and resources