The 74HC4020-Q100; 74HCT4020-Q100 is a 14-stage binary ripple counter with a clock input (CP), an overriding asynchronous master reset input (MR) and 12 buffered parallel outputs (Q0, and Q3 to Q13). The counter advances on the HIGH-to-LOW transition ofCP. A HIGH on MR clears all counter stages and forces all outputs LOW, independent of the state ofCP. Each counter stage is a static toggle flip-flop. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.