
CY62148ELL-45ZSXIT
ActiveSRAM, ASYNCHRONOUS SRAM, 4 MBIT, 512K X 8BIT, TSOP-II, 32 PINS, 4.5 V
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CY62148ELL-45ZSXIT
ActiveSRAM, ASYNCHRONOUS SRAM, 4 MBIT, 512K X 8BIT, TSOP-II, 32 PINS, 4.5 V
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Technical Specifications
Parameters and characteristics for this part
| Specification | CY62148ELL-45ZSXIT |
|---|---|
| Access Time | 45 ns |
| Memory Format | SRAM |
| Memory Interface | Parallel |
| Memory Organization | 512 K |
| Memory Size | 512 kb |
| Memory Type | Volatile |
| Mounting Type | Surface Mount |
| Operating Temperature [Max] | 85 °C |
| Operating Temperature [Min] | -40 °C |
| Package / Case | 32-SOIC |
| Package / Case [x] | 0.4 in |
| Package / Case [y] | 10.16 mm |
| Supplier Device Package | 32-TSOP II |
| Technology | SRAM - Asynchronous |
| Voltage - Supply [Max] | 5.5 V |
| Voltage - Supply [Min] | 4.5 V |
| Write Cycle Time - Word, Page [custom] | 45 ns |
| Write Cycle Time - Word, Page [custom] | 45 ns |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Cut Tape (CT) | 1 | $ 8.47 | |
| 10 | $ 7.80 | |||
| 25 | $ 7.63 | |||
| 50 | $ 7.61 | |||
| 100 | $ 6.83 | |||
| 250 | $ 6.62 | |||
| 500 | $ 6.30 | |||
| Digi-Reel® | 1 | $ 8.47 | ||
| 10 | $ 7.80 | |||
| 25 | $ 7.63 | |||
| 50 | $ 7.61 | |||
| 100 | $ 6.83 | |||
| 250 | $ 6.62 | |||
| 500 | $ 6.30 | |||
| Tape & Reel (TR) | 1000 | $ 6.08 | ||
| Newark | Each (Supplied on Cut Tape) | 1 | $ 8.90 | |
| 10 | $ 8.02 | |||
| 25 | $ 7.38 | |||
| 50 | $ 7.25 | |||
| 100 | $ 7.10 | |||
| 250 | $ 6.79 | |||
| 500 | $ 6.50 | |||
| 1000 | $ 5.56 | |||
Description
General part information
CY62148 Series
CY62148ELL-45ZSXIT is a high performance CMOS static RAM organized as 512K words by 8-bits. This device features an advanced circuit design to provide ultra-low standby current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption when addresses are not toggling. Placing the device into standby mode reduces power consumption by more than 99% when deselected (active-low CE HIGH). The eight input and output pins (I/O0 through I/O7) are placed in a high impedance state when the device is deselected (active-low CE HIGH), outputs are disabled (active-low OE HIGH), or during an active write operation (active-low CE LOW and active-low WE LOW). It is suitable for interfacing with processors that have TTL I/P levels.
Documents
Technical documentation and resources