SY100EL92ZG
ActiveIC TRANSLATOR UNIDIR 20SOIC
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SY100EL92ZG
ActiveIC TRANSLATOR UNIDIR 20SOIC
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Technical Specifications
Parameters and characteristics commom to parts in this series
| Specification | SY100EL92ZG | 100EL92 Series |
|---|---|---|
| Channel Type | Unidirectional | Unidirectional |
| Channels per Circuit | 3 | 3 |
| Input Signal | LVPECL, PECL | LVPECL, PECL |
| Mounting Type | Surface Mount | Surface Mount |
| Number of Circuits | 1 | 1 |
| Operating Temperature [Max] | 85 °C | 85 °C |
| Operating Temperature [Min] | -40 °C | -40 - 0 °C |
| Output Signal | LVPECL, PECL | LVPECL, PECL |
| Output Type | Differential | Differential |
| Package / Case | 20-SOIC | 20-SOIC |
| Package / Case [y] | 0.295 in | 0.295 in |
| Package / Case [y] | 7.5 mm | 7.5 mm |
| Supplier Device Package | 20-SOIC | 20-SOIC |
| Translator Type | Mixed Signal | Mixed Signal |
Pricing
Prices provided here are for design reference only. For realtime values and availability, please visit the distributors directly
| Distributor | Package | Quantity | $ | |
|---|---|---|---|---|
| Digikey | Tube | 228 | $ 4.50 | |
| Microchip Direct | TUBE | 1 | $ 5.59 | |
| 25 | $ 4.66 | |||
| 100 | $ 4.24 | |||
| 1000 | $ 4.09 | |||
| 5000 | $ 4.04 | |||
| 10000 | $ 4.00 | |||
100EL92 Series
IC TRANSLATOR UNIDIR 20SOIC
| Part | Channel Type | Output Signal | Supplier Device Package | Translator Type | Output Type | Input Signal | Mounting Type | Package / Case | Package / Case [y] | Package / Case [y] | Number of Circuits | Operating Temperature [Max] | Operating Temperature [Min] | Channels per Circuit |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Microchip Technology SY100EL92ZI | Unidirectional | LVPECL, PECL | 20-SOIC | Mixed Signal | Differential | LVPECL, PECL | Surface Mount | 20-SOIC | 0.295 in | 7.5 mm | 1 | 85 °C | -40 °C | 3 |
Microchip Technology SY100EL92ZG | Unidirectional | LVPECL, PECL | 20-SOIC | Mixed Signal | Differential | LVPECL, PECL | Surface Mount | 20-SOIC | 0.295 in | 7.5 mm | 1 | 85 °C | -40 °C | 3 |
Microchip Technology SY100EL92ZC-TR | Unidirectional | LVPECL, PECL | 20-SOIC | Mixed Signal | Differential | LVPECL, PECL | Surface Mount | 20-SOIC | 0.295 in | 7.5 mm | 1 | 85 C | 0 °C | 3 |
Microchip Technology SY100EL92ZC | Unidirectional | LVPECL, PECL | 20-SOIC | Mixed Signal | Differential | LVPECL, PECL | Surface Mount | 20-SOIC | 0.295 in | 7.5 mm | 1 | 85 C | 0 °C | 3 |
Description
General part information
100EL92 Series
The SY100EL92 is a triple LVPECL-to-PECL or PECLto-LVPECL translator. The device receives standard PECL signals and translates them to differential LVPECL output signals (or vice versa). SY100EL92 can also be used as a differential line receiver for PECL-to-PECL or LVPECL-to-LVPECL signals. However, please note that for the latter we will need two different power supplies. Please refer to Function Table for more details.VBB outputs are provided for interfacing single ended input signals. If a single ended input is to be used, the VBB output should be connected to the D input and the active signal will drive the D input. When used, the VBB should be bypassed to VCC via a 0.01µF capacitor.
The VBB is designed to act as a switching reference for the SY100EL92 under single ended input conditions. As a result, the pin can only source/sink 0.5mA of current.To accomplish the PECL-to-LVPECL level translation, the SY100EL92 requires three power rails. The VCC and VCC\_VBB supply is to be connected to the standard PECL supply, the 3.3V supply is to be connected to the VCCOsupply, and GND is connected to the system ground plane.
Both the VCC and VCCO should be bypassed to ground with a 0.01µF capacitor.To accomplish the LVPECL-to-PECL level translation, the SY100EL92 requires three power rails as well. The 5.0V supply is connected to the VCC and VCCO pins, 3.3V supply is connected to the VCC\_VBB pin and GND is connected to the system ground plane. VCC\_VBB is used to provide a proper VBB output level if a single ended input is used. For differential LVPECL input VCC\_VBB can be either 3.3V or 5V.Under open input conditions, the D input will be biased at a VCC/2 voltage level and the D input will be pulled to GND. This condition will force the "Q" output low, ensuring stability.
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