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ADSP-21363KSWZ-1AA

ADSP-21363KSWZ-1AA

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Analog Devices Inc./Maxim Integrated

DIGITAL SIGNAL PROCESSORS & CONTROLLERS - DSP, DSC 333 MHZ.PROCW/ON CHIP BLANKROM EPAD PBFR

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ADSP-21363KSWZ-1AA

ADSP-21363KSWZ-1AA

Active
Analog Devices Inc./Maxim Integrated

DIGITAL SIGNAL PROCESSORS & CONTROLLERS - DSP, DSC 333 MHZ.PROCW/ON CHIP BLANKROM EPAD PBFR

Find alt

Description

General part information

ADSP-21363 Series

The third generation of SHARC®Processors, which includes theADSP-21261,ADSP-21262,ADSP-21266, ADSP-21363,ADSP-21364,ADSP-21365, andADSP-21366offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible with each other and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.The ADSP-21363 offers the highest performance – 333 MHz/2 GFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21363 particularly well suited to address the increasing requirements of many general purpose signal processing applications.Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include, but are not limited to, serial ports, SPI ports and an 8-Channel asynchronous sample rate converter block.

Technical Specifications

Parameters and characteristics for this part

SpecificationADSP-21363KSWZ-1AA
Clock Rate (Frequency)333 MHz
InterfaceSPI, DAI
Mounting TypeSurface Mount
Non-Volatile Memory Size512 kB
Non-Volatile Memory TypeROM
On-Chip RAM384 kB
Operating Temperature (Max)70 °C
Operating Temperature (Min)0 °C
Package / Case144-LQFP Exposed Pad
Package Length20 mm
Package Name144-LQFP-EP
Package Width20 mm
TypeFloating Point
Voltage - Core1.2 V
Voltage - I/O3.3 V

Pricing

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CAD

3D models and CAD resources for this part

Documents

Technical documentation and resources

EE-332: Cycle Counting and Profiling (Rev.2)
ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARC Processors (Rev.J)
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++
EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev.2)
VisualDSP++®5.0 C/C++ Compiler Manual for SHARC®Processors (Rev.1.5)
EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev.2)
EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev.1)
EE-290: Managing the Core PLL on SHARC® Processors (Rev.5)
VisualDSP++®5.0 Assembler and Preprocessor Manual (Rev.3.4)
EE-254: Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (Rev.1)
EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev.1)
VisualDSP++®5.0 Run-Time Library Manual for SHARC®Processors (Rev.1.5)
ICE-100B Emulator User’s Guide (Rev.1.1)
ADSP-2136x SHARC®Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) (Rev.2.1)
EE-220: Using External Memory with Third Generation SHARC® Processors and the Parallel Port (Rev.2)
EE-340: Connecting SHARC®and Blackfin®Processors over SPI (Rev.1)
EE-268: Programming Asynchronous Sample Rate Converters on ADSP-2136x SHARC® Processors (Rev.1)
EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev.1)
EE-231: In-Circuit Programming of an SPI Flash with SHARC® Processors (Rev.2)
EE-295: Implementing Delay Lines on SHARC® Processors (Rev.1)
SHARC®Audio EZ-Extender®Manual (Rev.1.1)
EE-345: Boot Kernel Customization and Firmware Upgradeability on SHARC Processors® (Rev.1)
EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev.1)
EE-230: Code Overlays on the Third Generation SHARC® Family of Processors (Rev.2)
HPUSB, USB, and HPPCI Emulator User’s Guide (Rev.3.2)
SHARC Processor Family
ICE-1000/ICE-2000 Emulator User’s Guide (Rev.1.2)
EE-322: Expert Code Generator for SHARC® Processors (Rev.5)
SHARC®EZ-Extender®Manual (Rev.3.1)
EE-323: Implementing Dynamically Loaded Software Modules (Rev.1)
EE-248: Interfacing AD7676 ADCs to ADSP-21365 SHARC® Processors (Rev.1)
VisualDSP++®5.0 Licensing Guide (Rev.1.4)
EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev.1)
EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs
EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs
EE-104: Setting Up Streams with the VisualDSP Debugger
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev.3)
VisualDSP++®5.0 Users Guide (Rev.3.0)
SHARC®USB EZ-Extender®Manual (Rev.2.1)
EE-320: Implementing an Ogg Vorbis Decoder on SHARC® Processors (Rev.1)
EE-110: A Quick Primer on ELF and DWARF File Formats
EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev.1)
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev.1)
EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev.1)
EE-277: Estimating Power for the ADSP-21362 SHARC® Processors (Rev.1)
VisualDSP++®5.0 Quick Installation Reference Card (Rev.3.1)
EE-266: Programming S/PDIF on ADSP-2136x and ADSP-21371 SHARC® Processors (Rev.2)
Blackfin®/SHARC®USB EZ-Extender®Manual (Rev.1.1)
VisualDSP++®5.0 Getting Started Guide (Rev.3.0)
SHARC®Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx Processors) (Rev.2.4)
EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev.3)
VisualDSP++®5.0 Kernel (VDK) Users Guide (Rev.3.5)
EE-253: Power Bypass Decoupling of SHARC® Processors (Rev.1)
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev.10)
EE-305: Designing and Debugging Systems with SHARC Processors (Rev.1)
VisualDSP++®5.0 Product Release Bulletin (Rev.3.0)
EE-296: Using the UART Port Controller on SHARC® Processors (Rev.2)
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev.14)
EE-177: SHARC® SPI Slave Booting (Rev.3)
Package Drawing - 144-Lead LQFP (10mm x 10mm w/ EP)
VisualDSP++®5.0 Linker and Utilities Manual (Rev.3.5)
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev.1)
VisualDSP++®5.0 Loader and Utilities Manual (Rev.2.5)
    ADSP-21363KSWZ-1AA | Analog Devices Inc./Maxim Integrated | Zenode.ai